barrel_shifter.vo

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// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.1 Build 201 11/27/2006 SJ Full Version"

// DATE "10/26/2007 16:11:25"

// 
// Device: Altera EP2C5F256C6 Package FBGA256
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module barrel_shifter (
	dataout,
	datain,
	reset,
	ld,
	clk);
output 	[7:0] dataout;
input 	[7:0] datain;
input 	reset;
input 	ld;
input 	clk;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("barrel_shifter_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \clk~clkctrl ;
wire \ld~combout ;
wire \dataout~97 ;
wire \reset~combout ;
wire \reset~clkctrl ;
wire \dataout[1]~reg0 ;
wire \dataout~98 ;
wire \dataout[2]~reg0 ;
wire \dataout~99 ;
wire \dataout[3]~reg0 ;
wire \dataout~100 ;
wire \dataout[4]~reg0 ;
wire \dataout~101 ;
wire \dataout[5]~reg0 ;
wire \dataout~102 ;
wire \dataout[6]~reg0 ;
wire \dataout~103 ;
wire \dataout[7]~reg0 ;
wire \dataout~96 ;
wire \dataout[0]~reg0 ;
wire [7:0] \datain~combout ;


// atom is at PIN_M1
cycloneii_io \datain[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [0]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[0]));
// synopsys translate_off
defparam \datain[0]~I .input_async_reset = "none";
defparam \datain[0]~I .input_power_up = "low";
defparam \datain[0]~I .input_register_mode = "none";
defparam \datain[0]~I .input_sync_reset = "none";
defparam \datain[0]~I .oe_async_reset = "none";
defparam \datain[0]~I .oe_power_up = "low";
defparam \datain[0]~I .oe_register_mode = "none";
defparam \datain[0]~I .oe_sync_reset = "none";
defparam \datain[0]~I .operation_mode = "input";
defparam \datain[0]~I .output_async_reset = "none";
defparam \datain[0]~I .output_power_up = "low";
defparam \datain[0]~I .output_register_mode = "none";
defparam \datain[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_P5
cycloneii_io \datain[6]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [6]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[6]));
// synopsys translate_off
defparam \datain[6]~I .input_async_reset = "none";
defparam \datain[6]~I .input_power_up = "low";
defparam \datain[6]~I .input_register_mode = "none";
defparam \datain[6]~I .input_sync_reset = "none";
defparam \datain[6]~I .oe_async_reset = "none";
defparam \datain[6]~I .oe_power_up = "low";
defparam \datain[6]~I .oe_register_mode = "none";
defparam \datain[6]~I .oe_sync_reset = "none";
defparam \datain[6]~I .operation_mode = "input";
defparam \datain[6]~I .output_async_reset = "none";
defparam \datain[6]~I .output_power_up = "low";
defparam \datain[6]~I .output_register_mode = "none";
defparam \datain[6]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_H2
cycloneii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G2
cycloneii_clkctrl \clk~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\clk~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clk~clkctrl ));
// synopsys translate_off
defparam \clk~clkctrl_I .clock_type = "global clock";
defparam \clk~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_K15
cycloneii_io \ld~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\ld~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(ld));
// synopsys translate_off
defparam \ld~I .input_async_reset = "none";
defparam \ld~I .input_power_up = "low";
defparam \ld~I .input_register_mode = "none";
defparam \ld~I .input_sync_reset = "none";
defparam \ld~I .oe_async_reset = "none";
defparam \ld~I .oe_power_up = "low";
defparam \ld~I .oe_register_mode = "none";
defparam \ld~I .oe_sync_reset = "none";
defparam \ld~I .operation_mode = "input";
defparam \ld~I .output_async_reset = "none";
defparam \ld~I .output_power_up = "low";
defparam \ld~I .output_register_mode = "none";
defparam \ld~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_D6
cycloneii_io \datain[7]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [7]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[7]));
// synopsys translate_off
defparam \datain[7]~I .input_async_reset = "none";
defparam \datain[7]~I .input_power_up = "low";
defparam \datain[7]~I .input_register_mode = "none";
defparam \datain[7]~I .input_sync_reset = "none";
defparam \datain[7]~I .oe_async_reset = "none";
defparam \datain[7]~I .oe_power_up = "low";
defparam \datain[7]~I .oe_register_mode = "none";
defparam \datain[7]~I .oe_sync_reset = "none";
defparam \datain[7]~I .operation_mode = "input";
defparam \datain[7]~I .output_async_reset = "none";
defparam \datain[7]~I .output_power_up = "low";
defparam \datain[7]~I .output_register_mode = "none";
defparam \datain[7]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J1
cycloneii_io \datain[5]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [5]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[5]));
// synopsys translate_off
defparam \datain[5]~I .input_async_reset = "none";
defparam \datain[5]~I .input_power_up = "low";
defparam \datain[5]~I .input_register_mode = "none";
defparam \datain[5]~I .input_sync_reset = "none";
defparam \datain[5]~I .oe_async_reset = "none";
defparam \datain[5]~I .oe_power_up = "low";
defparam \datain[5]~I .oe_register_mode = "none";
defparam \datain[5]~I .oe_sync_reset = "none";
defparam \datain[5]~I .operation_mode = "input";
defparam \datain[5]~I .output_async_reset = "none";
defparam \datain[5]~I .output_power_up = "low";
defparam \datain[5]~I .output_register_mode = "none";
defparam \datain[5]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_J2
cycloneii_io \datain[4]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [4]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[4]));
// synopsys translate_off
defparam \datain[4]~I .input_async_reset = "none";
defparam \datain[4]~I .input_power_up = "low";
defparam \datain[4]~I .input_register_mode = "none";
defparam \datain[4]~I .input_sync_reset = "none";
defparam \datain[4]~I .oe_async_reset = "none";
defparam \datain[4]~I .oe_power_up = "low";
defparam \datain[4]~I .oe_register_mode = "none";
defparam \datain[4]~I .oe_sync_reset = "none";
defparam \datain[4]~I .operation_mode = "input";
defparam \datain[4]~I .output_async_reset = "none";
defparam \datain[4]~I .output_power_up = "low";
defparam \datain[4]~I .output_register_mode = "none";
defparam \datain[4]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_L2
cycloneii_io \datain[3]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [3]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[3]));
// synopsys translate_off
defparam \datain[3]~I .input_async_reset = "none";
defparam \datain[3]~I .input_power_up = "low";
defparam \datain[3]~I .input_register_mode = "none";
defparam \datain[3]~I .input_sync_reset = "none";
defparam \datain[3]~I .oe_async_reset = "none";
defparam \datain[3]~I .oe_power_up = "low";
defparam \datain[3]~I .oe_register_mode = "none";
defparam \datain[3]~I .oe_sync_reset = "none";
defparam \datain[3]~I .operation_mode = "input";
defparam \datain[3]~I .output_async_reset = "none";
defparam \datain[3]~I .output_power_up = "low";
defparam \datain[3]~I .output_register_mode = "none";
defparam \datain[3]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_T3
cycloneii_io \datain[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [2]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[2]));
// synopsys translate_off
defparam \datain[2]~I .input_async_reset = "none";
defparam \datain[2]~I .input_power_up = "low";
defparam \datain[2]~I .input_register_mode = "none";
defparam \datain[2]~I .input_sync_reset = "none";
defparam \datain[2]~I .oe_async_reset = "none";
defparam \datain[2]~I .oe_power_up = "low";
defparam \datain[2]~I .oe_register_mode = "none";
defparam \datain[2]~I .oe_sync_reset = "none";
defparam \datain[2]~I .operation_mode = "input";
defparam \datain[2]~I .output_async_reset = "none";
defparam \datain[2]~I .output_power_up = "low";
defparam \datain[2]~I .output_register_mode = "none";
defparam \datain[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_A3
cycloneii_io \datain[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\datain~combout [1]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(datain[1]));
// synopsys translate_off
defparam \datain[1]~I .input_async_reset = "none";
defparam \datain[1]~I .input_power_up = "low";
defparam \datain[1]~I .input_register_mode = "none";
defparam \datain[1]~I .input_sync_reset = "none";
defparam \datain[1]~I .oe_async_reset = "none";
defparam \datain[1]~I .oe_power_up = "low";
defparam \datain[1]~I .oe_register_mode = "none";
defparam \datain[1]~I .oe_sync_reset = "none";
defparam \datain[1]~I .operation_mode = "input";
defparam \datain[1]~I .output_async_reset = "none";
defparam \datain[1]~I .output_power_up = "low";
defparam \datain[1]~I .output_register_mode = "none";
defparam \datain[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCCOMB_X1_Y6_N0
cycloneii_lcell_comb \dataout~97_I (
// Equation(s):
// \dataout~97  = \ld~combout  & \datain~combout [1] # !\ld~combout  & (\dataout[0]~reg0 )

	.dataa(\ld~combout ),
	.datab(\datain~combout [1]),
	.datac(vcc),
	.datad(\dataout[0]~reg0 ),
	.cin(gnd),
	.combout(\dataout~97 ),
	.cout());
// synopsys translate_off
defparam \dataout~97_I .lut_mask = 16'hDD88;
defparam \dataout~97_I .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_H1
cycloneii_io \reset~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\reset~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(reset));
// synopsys translate_off
defparam \reset~I .input_async_reset = "none";
defparam \reset~I .input_power_up = "low";
defparam \reset~I .input_register_mode = "none";
defparam \reset~I .input_sync_reset = "none";
defparam \reset~I .oe_async_reset = "none";
defparam \reset~I .oe_power_up = "low";
defparam \reset~I .oe_register_mode = "none";
defparam \reset~I .oe_sync_reset = "none";
defparam \reset~I .operation_mode = "input";
defparam \reset~I .output_async_reset = "none";
defparam \reset~I .output_power_up = "low";
defparam \reset~I .output_register_mode = "none";
defparam \reset~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G1
cycloneii_clkctrl \reset~clkctrl_I (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\reset~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\reset~clkctrl ));
// synopsys translate_off
defparam \reset~clkctrl_I .clock_type = "global clock";
defparam \reset~clkctrl_I .ena_register_mode = "falling edge";
// synopsys translate_on