afifo_2.v

FIFO 经过多次修改及上板调试 可放心使用 本人也在学习之中

//FILE NAME: aFifo_2
//AUTHOR:    jialiang

`timescale 1ns/1ns
module aFifo_2(
     data_out,
     empty,
     full,
     data_in,
     clk_read,
     read,
     clk_write,
     write,
     rst);

    parameter    DATA_WIDTH    = 8;
    parameter    ADDRESS_WIDTH = 6;
    parameter    FIFO_DEPTH    = 64;
    
    output   [DATA_WIDTH-1:0]        data_out; 
    output                           empty;
    output                           full; 
    input    [DATA_WIDTH-1:0]        data_in;
    input                            clk_read;
    input                            read;        
    input                            clk_write;
    input                            write;
    input                            rst ;

    reg  [DATA_WIDTH-1:0]        data_out;
    wire                         empty;
    wire                         full;

    /////Internal connections & variables//////
    reg   [DATA_WIDTH-1:0]              mem [FIFO_DEPTH-1:0];
    wire  [ADDRESS_WIDTH:0]             write_ptr;
    wire  [ADDRESS_WIDTH:0]             read_ptr;
    wire  [ADDRESS_WIDTH-1:0]           write_addr;
    wire  [ADDRESS_WIDTH-1:0]           read_addr;
    wire                                write_enable;
    wire                                read_enable;
    
    reg   [ADDRESS_WIDTH:0]  read_ptr_meta;
    reg   [ADDRESS_WIDTH:0]  read_ptr_write_synch;
    reg   [ADDRESS_WIDTH:0]  write_ptr_meta;
    reg   [ADDRESS_WIDTH:0]  write_ptr_read_synch;

    //mem logic
    always @(posedge clk_read) begin
        if (read_enable) begin
            data_out <= mem[read_addr];
        end
    end
 
    always @(posedge clk_write) begin
        if (write_enable) begin
            mem[write_addr] <= data_in;
        end  
    end
 
    //Enable
    assign write_enable = write & ~full;
    assign read_enable  = read  & ~empty;
           
    //Addreses change to Gray code
    GrayCounter_2 GrayCounter_write
       (write_ptr,
        write_addr,       //get out a binary  value
        write_enable, 
        rst,
        clk_write);
       
    GrayCounter_2 GrayCounter_read
       (read_ptr, 
        read_addr,       //get out a binary value
        read_enable,
        rst,
        clk_read);

    //Read_ptr synchronizes to clk_write
    always @(posedge clk_write or negedge rst) begin
       if(!rst) begin
             read_ptr_meta <= 0;
             read_ptr_write_synch <= 0;
       end
       else begin
            read_ptr_meta        <= read_ptr;
            read_ptr_write_synch <= read_ptr_meta;
       end 
    end //End always @ (posedge clk_write or negedge rst)
    
    //Write_ptr synchronizes to clk_read
    always @(posedge clk_read or negedge rst) begin
        if(!rst) begin
            write_ptr_meta <= 0;
            write_ptr_read_synch <= 0;
        end
        else begin
            write_ptr_meta        <= write_ptr;
            write_ptr_read_synch  <= write_ptr_meta;
        end
    end
    
    //writing full
    assign full = (write_ptr[ADDRESS_WIDTH:ADDRESS_WIDTH-1] == 
                  ~read_ptr_write_synch[ADDRESS_WIDTH:ADDRESS_WIDTH-1]) &&
                  (write_ptr[ADDRESS_WIDTH-2:0] == 
                   read_ptr_write_synch[ADDRESS_WIDTH-2:0]);
                   
    //reading empty
    assign empty = (write_ptr_read_synch == read_ptr);
    
endmodule