fmd.cpp

It s wince for ARM9 evaluation board

     // Set up address
     //NF_ADDR_(0);	
     //NF_ADDR_(startSectorAddr<<8);    
     //NF_ADDR(0x00);
     //NF_ADDR((startSectorAddr) & 0xff);
     //NF_ADDR((startSectorAddr >> 8) & 0xff);
     // if (NEED_EXT_ADDR) {
     //NF_ADDR((startSectorAddr >> 16) & 0xff);
     //  }

  NF_LOCK_DISABLE();
  NF_ST_START();
  NF_STDONE_CHECK();
  NF_STDONE_CLEAR();   
  NF_CE_L();
  NF_DISABLE_ALLMODE(); 
  NF_SW_MODE();

   //Read out the ECC value generated by HW
  NF_MECC_Lock();
  dwECCVal = NF_ECC();  
 
#else
    //  Issue command
    NF_CMD(CMD_READ);
    NF_CMD(CMD_WRITE);

    //  Setup address
    NF_ADDR(0x00);
    NF_ADDR((startSectorAddr) & 0xff);
    NF_ADDR((startSectorAddr >> 8) & 0xff);

       if (NEED_EXT_ADDR) {
    NF_ADDR((startSectorAddr >> 16) & 0xff);
     }

    //  Special case to handle un-aligned buffer pointer.
    //
    if( ((DWORD) pSectorBuff) & 0x3) {
         //  Write the data
        for(i=0; i<SECTOR_SIZE; i++) {
            NF_DATA_W(pSectorBuff[i]);
        }
    }
    else {
        WritePage512(pSectorBuff, pNFDATA);
    }
	 //Read out the ECC value generated by HW
	NF_MECC_Lock();
       dwECCVal = NF_ECC();



#endif

#if 0
    NF_Reset();
//  Chip enable
    NF_CE_L();
    NF_CLEAR_RB();

    //  Write the command
    //  First, let's point to the spare area
    NF_CMD(CMD_READ2);
    NF_CMD(CMD_WRITE);

    //  Write the address
    NF_ADDR(0x00);
    NF_ADDR(startSectorAddr & 0xff);
    NF_ADDR((startSectorAddr >> 8) & 0xff);

 //   if (NEED_EXT_ADDR) {
        NF_ADDR((startSectorAddr >> 16) & 0xff);
  //  }
#endif

       //Read out the ECC value generated by HW
	//NF_MECC_Lock();
       //dwECCVal = NF_ECC();

	// Write the SectorInfo data to the media
	// NOTE: This hardware is odd: only a byte can be written at a time and it must reside in the
	//       upper byte of a USHORT.
	if(pSectorInfoBuff)
	{
        //  Write the first reserved field (DWORD)
        NF_DATA_W( (pSectorInfoBuff->dwReserved1 >> 24) & 0xff );
        NF_DATA_W( (pSectorInfoBuff->dwReserved1 >> 16) & 0xff );
        NF_DATA_W( (pSectorInfoBuff->dwReserved1 >> 8 ) & 0xff );
        NF_DATA_W( (pSectorInfoBuff->dwReserved1) & 0xff );

        //  Write OEM reserved flag
        NF_DATA_W( (pSectorInfoBuff->bOEMReserved) );

        //  Write the bad block flag
        NF_DATA_W( (pSectorInfoBuff->bBadBlock) );

        //  Write the second reserved field
        NF_DATA_W( (pSectorInfoBuff->wReserved2 >> 8) & 0xff );
        NF_DATA_W( (pSectorInfoBuff->wReserved2) & 0xff );

	}else
	{
		// Make sure we advance the Flash's write pointer (even though we aren't writing the SectorInfo data)
		for(i=0; i<sizeof(SectorInfo); i++)
		{
            NF_DATA_W(0xff);
		}
	}

    //  ECC stuff should be here
    eccBuf[0] = (BYTE) ((dwECCVal) & 0xff);
    eccBuf[1] = (BYTE) ((dwECCVal >> 8) & 0xff);
    eccBuf[2] = (BYTE) ((dwECCVal >> 16) & 0xff);

    //  Write the ECC value to the flash.$Byte number 520,521,522
    for(i=0; i<3; i++) {
        NF_DATA_W(eccBuf[i]);
    }

    for(i=0; i<5; i++) {     //$why writting FF here at all 523rd to 527th byte TBD
        NF_DATA_W(0xff);
    }

	NF_CLEAR_RB();  //$RnB transition is cleared.It means now onward as soon as RnB occurs it will make this bit to be one.
    //  Finish up the write operation
       NF_CMD(CMD_WRITE2);

    //  Wait for RB
	NF_DETECT_RB();	 // Wait tR(max 12us)
    //for(i=0;i<1000;i++);

	 s24A0IOP->rGPDAT &=~(1<<1);	

    //  Check the status
       NF_CMD(CMD_STATUS);

    if(NF_DATA_R() & STATUS_ERROR) {
#ifdef BOOT_LOADER
        EdbgOutputDebugString("FMD_WriteSector() ######## Error Programming page %d!\r\n", startSectorAddr);
#else
        RETAILMSG(1, (TEXT("FMD_WriteSector() ######## Error Programming page %d!\n"), startSectorAddr));
#endif

bRet = FALSE;
    }

    //  Disable the chip
    NF_CE_H();
    RELEASEMUTEX();

#if  0
if(j++<10) {
	FMD_ReadSector(startSectorAddr, rbuff,
                        pSectorInfoBuff, 1);
				RETAILMSG(1, (TEXT("Data in sector%d \r\n"),startSectorAddr));
				for(i=0; i<SECTOR_SIZE; i++){
				   RETAILMSG(1, (TEXT("R:%2x    "),rbuff[i]));	
				   //RETAILMSG(1, (TEXT("SteppingStone  :   ")));
				   //RETAILMSG(1, (TEXT("S:%2x    "),sbuff[i]));
				   RETAILMSG(1, (TEXT("W:%2x\r\n"),pSectorBuff[i]));
				   

				  if((i%8) == 0 )
				 	RETAILMSG(1, (TEXT("\r\n")));
				}
			}		
#endif	
    return bRet;
}

/*
 *  MarkBlockBad
 *
 *  Mark the block as a bad block. We need to write a 00 to the 517th byte
 */

BOOL MarkBlockBad(BLOCK_ID blockID)
{
    DWORD   dwStartPage = blockID << 5;
    BOOL    bRet = TRUE;

    DEBUGMSG(1, (TEXT("MarkBlockBad\r\n")));
    GRABMUTEX();
   	
    s24A0IOP->rGPCON_L=(s24A0IOP->rGPCON_L & ~(0x3<<2))|(0x1<<2);// Setting as OUTPUT Mode
    s24A0IOP->rGPDAT |=(1<<1);	
    //  Enable chip
    NF_CE_L();
    NF_CLEAR_RB();

    //  Issue command
    //  We are dealing with spare area
    NF_CMD(CMD_READ2);
    NF_CMD(CMD_WRITE);

    //  Set up address
    NF_ADDR(VALIDADDR);
    NF_ADDR((dwStartPage) & 0xff);
    NF_ADDR((dwStartPage >> 8) & 0xff);
      if (NEED_EXT_ADDR) {
    NF_ADDR((dwStartPage >> 16) & 0xff);
     }

    NF_DATA_W(BADBLOCKMARK);

    //  Complete the write
    NF_CMD(CMD_WRITE2);

    //  Wait for RB
    NF_DETECT_RB();	 // Wait tR(max 12us)


     s24A0IOP->rGPDAT &=~(1<<1);	
    //  Get the status
    NF_CMD(CMD_STATUS);

    if(NF_DATA_R() &  STATUS_ERROR) {
        RETAILMSG(1, (TEXT("######## Failed to mark the block bad!\n")));
        bRet = FALSE;
    }

    //  Disable chip select
    NF_CE_H();

    RELEASEMUTEX();
    return bRet;
}

//
//  FMD_SetBlockStatus
//
//  Sets the status of a block.  Only implement for bad blocks for now.
//  Returns TRUE if no errors in setting.
//
BOOL FMD_SetBlockStatus(BLOCK_ID blockID, DWORD dwStatus)
{
       SECTOR_ADDR sectorAddr = blockID << LOG_2_PAGES_PER_BLOCK;
	BYTE bStatus = 0;
	DEBUGMSG(1, (TEXT("FMD_SetBlockStatus\r\n")));

    if(dwStatus & BLOCK_STATUS_BAD)
	{
        if(!MarkBlockBad (blockID))
        {
            return FALSE;//$ Error in setting, conflict.
        }
    }

    // We don't currently support setting a block to read-only, so fail if request is
    // for read-only and block is not currently read-only.
    if(dwStatus & BLOCK_STATUS_READONLY)
	{
        if(!(FMD_GetBlockStatus(blockID) & BLOCK_STATUS_READONLY))
        {
            return FALSE;
        }
    }

    return TRUE;
}



#ifndef NOSYSCALL
//  We don't have to build the following interface functions for the
//  bootloader.
//

//  FMD_PowerUp
//
//  Performs any necessary powerup procedures...
//
VOID FMD_PowerUp(VOID)
{
   
	DEBUGMSG(1, (TEXT("FMD_PowerUp\r\n")));

        //  Reinit the NAND controller
        GRABMUTEX();
		 s24A0SROM->rSROM_BW |=(1<<9);	
		WRITE_REGISTER_ULONG(pNFCONF, (0<<22)|(TECH<<16)|(TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<3)|(0<<2)|(1<<1)|(1<<0));
		WRITE_REGISTER_ULONG(pNFCONT, (0<<16)|(0<<15)|(0<<14)|(0<<13)|(0<<12)|(0<<11)|(1<<10)|(1<<9)|\
                   (0<<8)|(1<<7)|(0<<4)|(0<<3)|(1<<2)|(3<<0));

        RELEASEMUTEX();
        
        //  Reset the controller			
        NF_Reset();
#ifdef CEDAR_ONLY
        // ++ CE 3.0 Specific Code. Not needed for 4.x +
        SetInterruptEvent(SYSINTR_POWERON);
        // -- CE 3.0 Specific Code. Not needed for 4.x +
#endif // CEDAR_ONLY
    
}


//  FMD_PowerDown
//
//  Performs any necessary powerdown procedures...
//
VOID FMD_PowerDown(VOID)
{
	DEBUGMSG(1, (TEXT("FMD_Powerdown\r\n")));
}


//  FMD_OEMIoControl
//
//  Used for any OEM defined IOCTL operations
//
BOOL  FMD_OEMIoControl(DWORD dwIoControlCode, PBYTE pInBuf, DWORD nInBufSize,
                       PBYTE pOutBuf, DWORD nOutBufSize, PDWORD pBytesReturned)
{

	DEBUGMSG(1, (TEXT("FMD_OEMIoControl\r\n")));
    switch(dwIoControlCode)
    {
        case IOCTL_FMD_UPDATEXIP_BEGIN:
            g_bTakeMutex = TRUE;
            break;
            
        case IOCTL_FMD_UPDATEXIP_END:
            g_bTakeMutex = FALSE;
            break;
            
        default:
	        RETAILMSG(1, (TEXT("FMD::FMD_OEMIoControl = 0x%x\n"), dwIoControlCode));
            return FALSE;
    }
	return TRUE;
}

#endif // NOSYSCALL



//------------------------------- Private Interface (NOT used by the FAL) --------------------------

//  FMD_GetOEMReservedByte
//
//  Retrieves the OEM reserved byte (for metadata) for the specified physical sector.
//
//
BOOL FMD_GetOEMReservedByte(SECTOR_ADDR physicalSectorAddr, PBYTE pOEMReserved)
{


    DEBUGMSG(1, (TEXT("FMD_GetOEMReservedByte\r\n")));
    GRABMUTEX();
    
    //  Enable chip select
    NF_CE_L();
    NF_CLEAR_RB();

    //  Issue command
    NF_CMD(CMD_READ2);

    //  Set up address
    NF_ADDR(OEMADDR); //$5TH BYTE AS BAD BLOCK INFO IS HERE.
    NF_ADDR((physicalSectorAddr) & 0xff);
    NF_ADDR((physicalSectorAddr >> 8) & 0xff);

      if (NEED_EXT_ADDR) {
    NF_ADDR((physicalSectorAddr >> 16) & 0xff);
     }

    //  Wait for the ready bit
    NF_DETECT_RB();	 // Wait tR(max 12us)

    //  Read the data
    *pOEMReserved = (BYTE) NF_DATA_R();

    //  Disable chip select
    NF_CE_H();

    RELEASEMUTEX();
	return TRUE;

}


//  FMD_SetOEMReservedByte
//
//  Sets the OEM reserved byte (for metadata) for the specified physical sector.
//
BOOL FMD_SetOEMReservedByte(SECTOR_ADDR physicalSectorAddr, BYTE bOEMReserved)
{
    BOOL    bRet = TRUE;
    DEBUGMSG(1, (TEXT("FMD_SetOEMReservedByte\r\n")));
    GRABMUTEX();

    	 s24A0IOP->rGPCON_L=(s24A0IOP->rGPCON_L & ~(0x3<<2))|(0x1<<2);// Setting as OUTPUT Mode
        s24A0IOP->rGPDAT |=(1<<1);	

    //  Enable chip select
    NF_CE_L();
    NF_CLEAR_RB();

    //  Issue command
    NF_CMD(CMD_READ2);
    NF_CMD(CMD_WRITE);

    //  Set up address
    NF_ADDR(OEMADDR);
    NF_ADDR((physicalSectorAddr) & 0xff);
    NF_ADDR((physicalSectorAddr >> 8) & 0xff);

    if (NEED_EXT_ADDR) {
    NF_ADDR((physicalSectorAddr >> 16) & 0xff);
    }

    //  Write the data
    NF_DATA_W(bOEMReserved);

    //  Complete the write
    NF_CMD(CMD_WRITE2);

    //  Wait for the ready bit
    NF_DETECT_RB();	 // Wait tR(max 12us)

    s24A0IOP->rGPDAT &=~(1<<1);	

    //  Read the status
    NF_CMD(CMD_STATUS);

    //  Check the status
    if(NF_DATA_R() & STATUS_ERROR) {
        RETAILMSG(1, (TEXT("######## Failed to set OEM Reserved byte!\n")));
        bRet = FALSE;
    }

    //  Disable chip select
    NF_CE_H();

    RELEASEMUTEX();
    return bRet;
}

//---------------------------------------- Helper Functions ----------------------------------------

//  Interface function for testing purpose.
//
BOOL FMD_ReadSpare(DWORD dwStartPage, LPBYTE pBuff, DWORD dwNumPages)
{
    DWORD   i, n;
    RETAILMSG(1, (TEXT("FMD_ReadSpare\r\n")));

    GRABMUTEX();

    //  Enable chip select
    NF_CE_L();
    NF_CLEAR_RB();

    //  Issue command
    NF_CMD(CMD_READ2);

    //  Set up address
    NF_ADDR(0x00);
    NF_ADDR((dwStartPage) & 0xff);
    NF_ADDR((dwStartPage >> 8) & 0xff);

    if (NEED_EXT_ADDR) {
    NF_ADDR((dwStartPage >> 16) & 0xff);
    }

    //  Wait for Ready bit
    NF_DETECT_RB();	 // Wait tR(max 12us)

    //  Now read out the data
    for(n=0; n<dwNumPages; n++) {
        //  Read the spare area
        for(i=0; i<16; i++) {
            pBuff[n*16+i] = (BYTE) NF_DATA_R();
             }
    NF_DETECT_RB();	 // Wait tR(max 12us)
    }

    NF_CE_H();

    RELEASEMUTEX();
    return TRUE;
}

void GRABMUTEX()
{
#ifdef NOSYSCALL
#ifndef BOOT_LOADER
    // we're in the kernel - always SC_WaitForMultiple
    SC_WaitForMultiple(1, &g_hMutex, TRUE, INFINITE);
#endif
#else
    if (g_bTakeMutex) {
        // we can do a normal WaitForSingleObject
        WaitForSingleObject(g_hMutex, INFINITE);
    }
#endif
}

void RELEASEMUTEX()
{
#ifdef NOSYSCALL
#ifndef BOOT_LOADER
    SC_ReleaseMutex(g_hMutex);
#endif
#else
    if (g_bTakeMutex) {
        ReleaseMutex(g_hMutex);
    }
#endif
}