ss_syn.asm

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#include "SS_SYN.h"
//#define DEBUG_LINKPORT
//#define DEBUG_MODE2_FRAME_DATA 
#define DEBUG_AD3
//#define DEBUG_AD1
#define DEBUG_COMP_WITH_TH

///////////////////////extern function declaration////////////////////////////////
.extern _system_func;
.extern _null_func;
.extern _wait_cycles;

.extern JStack;
.extern KStack; 
.extern int_counter;
.extern Save_INTCTL;

#ifdef DEBUG_GEN_DATA
	.extern I1;
	.extern Q1;
	.extern IQ1;
#endif
.extern qout_o;
.extern qout_e;
.extern Pointer0;
.extern Pointer1;
.extern Ant_Data0;
.extern Ant_Data1;
.extern Ant_Data2;
.extern Ant_Data3;
.extern	Receive_Link0_TCB;
.extern	Receive_Link1_TCB;
.extern	Receive_Link2_TCB;
.extern	Receive_Link3_TCB;
.extern q_time_code;
.extern xcorrs_result_X;
.extern xcorrs_result_Y;
.extern _change_linkport_TCB;
////////////////////////////////////////
.extern _user_initial;

////////////////////////////////////////



//*********************************************************************//

.section program;
_power_up: 
//.align_code 4; jump _xcorrs_two_codes_one_frame;;
//*********************************************************************//
#ifdef __ADSPTS201__

/*in the case of TS201, at the beginning of the program the
cache must be enabled. The procedure is contained in the
cache_enable macro that uses the refresh rate as input parameter
      -if CCLK=500MHz, refresh_rate=750
      -if CCLK=400MHz, refresh_rate=600
      -if CCLK=300MHz, refresh_rate=450
      -if CCLK=250MHz, refresh_rate=375
*/

  cache_enable(600);

//-------------Optional example to preload cache-----------------------------

    j4 =Ant_Data0;;
    LC0 = 1152 ;;
    nop;;
.align_code 4;
ini_cache:    
	xr3:0 = q[j4+=0];;
.align_code 4;
    if NLC0E, jump ini_cache; q[j4+=4] = xr3:0;;

//----------------------------------------------------------------------------

#endif

 //-------------   base initial -----------------
 
 _DISABLE_HARDWARE_INTERRUPTS:

 XR0=0;;
 IMASKH=XR0;;
 IMASKL=XR0;;
 XR1=IMASKL;;
 XR1=XR1;;  

 //xr0=0x381041;;
 xr0=0x3819e7;;
 //xr0=0x381067;;
 syscon= xr0;;
 xr0=r0 xor r0;;
 sdrcon=xr0;;
 
 
 j0=pRead_Enable_clear;;
 k0=1;;
 [j0+j31]=k0;;
 j0=pRead_End;;
 [j0+j31]=k0;;

 

 j27=JStack;;
 k27=KStack;;
.align_code 4;
 call _system_func;q[J27+4]=J27:24;q[k27+4]=k27:24;;
 nop;;
 
 .align_code 4;
 call _null_func;;
 
.align_code 4;
_SET_INTCTL_REG:

 R0=0X0;;
 INTCTL=xR0;[ j31 + Save_INTCTL ]=yR0;;
 
 
_ENABLE_HARDWARE_INTERRUPTS:
 
 SQCTLST=SQCTL_GIE;;     
 nop;;
 
 /////////////////////for debug////////////////////////////
 
 		xmr1:0=r1:0;;
 		xr0=compact mr1:0;;
			
 ///////////////////////////////////////////////////////////
 //-------------   user initial ------------------
 
  
_after_reset: 

 XR0=0;;
 IMASKH=XR0;;
 IMASKL=XR0;;
 XR1=IMASKL;;
 XR1=XR1;;
 
 j27=JStack;;
 k27=KStack;;
 
 
 _Disable_Linkport_Input_first:
     
	r0=1;;
	#ifdef DEBUG_AD1
 	[ j31 + Stop_Linkport_AD1 ]=xr0;;
 	#endif
 	#ifdef DEBUG_AD3
 	[ j31 + Stop_Linkport_AD3 ]=xr0;;
 	#endif
 	//配置SS
 	[j31+SS_IND_ADDRESS]=xr0;;
 	//j4 = 320000*2 ;; 
	j4=1000;;
  	.align_code 4;
 	call _wait_cycles;;
  
 
 
 nop;;
 nop;;
.align_code 4;
call _user_initial;;                                    // _initial_Interface                     
                                                         //_initial_Received_TCB
                     
.align_code 4;                                                         
call _change_linkport_TCB;;                                                         
 .align_code 4;
// call  _release_all;;

                       
//-----------------  for debug function ----------------------- 
 
 
 //--------------  sys  initial -------------------
 
 _SET_INTERRUPT_VECTOR:
 
 j0=irq0_svr;;
 IVIRQ0=j0;;
 j0=dma0_svr;;
 IVDMA0=j0;;
 j0=dma1_svr;;
 IVDMA1=j0;;
 
 _UNMASK_INTERRUPT:
 
 xr0=IMASKH;;
 XR1=INT_IRQ0;;
 XR0=R0 OR R1;;
 IMASKH=XR0;;
 xr0=IMASKL;;
 XR1=INT_DMA0|INT_DMA1;;
 XR0=R0 OR R1;;
 IMASKL=XR0;;
 
_INITIAL_LINKPORT: 

 xr0=r0 xor r0;;
 LRCTL0=xr0;;
 LRCTL1=xr0;;
 nop;;nop;;nop;;nop;;nop;;
 xr0=LRCTL_REN  |  LRCTL_RDSIZE  ;;
 LRCTL0=xr0;;
 LRCTL1=xr0;;
 
_enable_flag_out:
             
       
  FLAGREGST= FLAGREG_FLAG3_EN;;
 xr0 = FLAGREG;;
 xr0 = bset r0 by FLAGREG_FLAG3_EN_P;;
 flagreg = xr0;;  
 
 yr0 = FLAGREG;;
 yr0 = btgl r0 by FLAGREG_FLAG3_OUT_P;;
flagreg = yr0;;

nop;;nop;;nop;; idle;;

 /////////////////////////////////first load data from linkport////////
 		r0=1;;
 		[j31+LINKPORT_MODE ]=xr0;;
 		[j31+linkport_mode_bak ]=xr0;; 
 		r0=0;;
 		[j31+linkport_timing ]=xr0;; 		
 		[j31+Bts_sim_timing ]=xr0;;
 		r0=1;;
 		#ifdef DEBUG_AD3
		[ j31 + Stop_Linkport_AD3]=xr0;; //stop signal		
		#endif
		#ifdef DEBUG_AD1		
		[ j31 + Stop_Linkport_AD1 ]=xr0;;
		#endif
 
 clear_data_in_Linkport_Buffer:
 
          xlr3:2=r3:2 xor r3:2;;
 		  xlr1:0=r1:0 xor r1:0;;
 
 		  DC8 = xr3:0;;   
 		  DC9 = xr3:0;;
 
 	      xr0=Ant_Data0;;
  	 	  xr1=SAMPLE_SEQUENCE_LENGTH<<16|4;;
  	 	  xr2=0;;
  	 	  xr3=TCB_INTMEM|TCB_QUAD|TCB_DMA8DEST;;               
          DC8 = xr3:0;;
          
          xr0=Ant_Data0+SAMPLE_SEQUENCE_LENGTH;;
  	 	  xr1=SAMPLE_SEQUENCE_LENGTH<<16|4;;
  	 	  xr2=0;;
  	 	  xr3=TCB_INTMEM|TCB_QUAD|TCB_DMA9DEST;;               
          DC9 = xr3:0;;
      
 clear_data_in_Linkport_Buffer_end:
  
 		  nop;; nop;; nop;;idle ;;
		  nop;; nop;; nop;;idle ;;
		  
		  
 	
  
.align_code 4; 
 _LOAD_TCB_TO_RECEIVE_DATA :    		 
          xlr3:2=r3:2 xor r3:2;;
 		  xlr1:0=r1:0 xor r1:0;; //clear control words
 		  DC8 = xr3:0;;   
 		  DC9 = xr3:0;;
		  nop;;
 		  nop;;
 		  
 		  j0=[j31+linkport_mode_bak ];;
 		  comp(j0,1);;
 		  .align_code 4;
 		  if njeq, jump _tcb_mode_2;;
 		  
 		  .align_code 4;
 		  _tcb_mode_1: 
 		   
			  j0=Ant_Data0;;
			  j1=Ant_Data1;;  
			  [ j31 + Pointer0 ] = j0 ;;   
			  [ j31 + Pointer1 ] = j1 ;;

	 		  j0=Receive_Link1_TCB;;
			  xr3:0 = q[ j0 + j31 ];;//fetch the control words		  
			  DC9 = xr3:0;;		//write control words
	 		  nop;;        
	 		  
	 		  j0=Receive_Link0_TCB;;
			  xr3:0 = q[ j0 + j31 ];;//fetch the control words		  
	 		  DC8 = xr3:0;;  	//write control words
	 		  nop;;
 		  .align_code 4;
 		  jump _tcb_end;;
 		  
 		  .align_code 4;
 		  _tcb_mode_2: 
 		  
 		  	  j0=Ant_Data2;;
			  j1=Ant_Data3;;  
			  [ j31 + Pointer0 ] = j0 ;;   
			  [ j31 + Pointer1 ] = j1 ;;
	 	
			  j0=Receive_Link3_TCB;;
			  xr3:0 = q[ j0 + j31 ];;//fetch the control words		  
			  DC9 = xr3:0;;		//write control words
	 		  nop;;        
	 		  
	 		  j0=Receive_Link2_TCB;;
			  xr3:0 = q[ j0 + j31 ];;//fetch the control words		  
	 		  DC8 = xr3:0;;  	//write control words
	 		  nop;;
 		  
 		  .align_code 4;
 		  _tcb_end: 
 		  
		  xr0 = 1;;
		#ifdef DEBUG_AD3
		[ j31 + Start_Linkport_AD3]=xr0;; 		
		#endif
		#ifdef DEBUG_AD1		
		[ j31 + Start_Linkport_AD1 ]=xr0;;
		#endif
		  nop;;nop;;nop;;idle;;		  
_LOAD_TCB_TO_RECEIVE_DATA_END:

	  		  
 		 
//loop and wait interrupt
.align_code 4;
_one_intr:
nop;;nop;;nop;;idle;;

.align_code 4;
	call _cp_track;;

///////////////DEBUG_LINKPORT//////////////////////////////////
#ifdef DEBUG_LINKPORT

	nop;nop;nop;nop;;			// break here

	j0=[ j31+linkport_mode_bak ];;
 	comp(j0,1);;
 	.align_code 4;
 	if njeq, jump _debug_linkprot_mode_2;;
 	
 	
 	//_mode_1:
	j4=[ j31+Pointer0 ];;
	j4=j4+Path_Window_Length ;;//指向天线数据Sample0 
	j5=j4+0x10000 ;;//Sample1
	j6=j4+SAMPLE_SEQUENCE_LENGTH ;;//Sample2