ss_syn.h

这是我在ADSP tiger sharc 201上面实现的OFDM(标准是wimax)同步算法哦!具有非常高的指令效率.

#if !defined	_SS_SYN_H_
#define			_SS_SYN_H_

#include "defts201.h"
#include "_divide.inc"
#include "cache_macros.h"

#define Version      0x6000
//---------define refresh rate----------------------------------

/////////////////address define///////////////////////////////////
#define	SYN_DSP_OFFSET								P3_OFFSET_LOC
#define SYN_DSP_Link_addr1							0x040000
#define SYN_DSP_Link_addr2							0x080000
#define SYN_DSP_Link_addr3							0x0C0000
#define SYN_DSP_Link_addr4							0x100000

//////////////////constant define/////////////////////////////////
#define XCORR_TH									0
//linkport parameters/////////////////////////////////////////////
#define Chips_in_One_Buffer          				64
#define Modify_RLinkport                            0x00004
#define Sample_Times                                0x00004

#define Path_Window_Length           				20
#define Times_Receive_One_Slot_Data  				446//28560/64=446.25
#define SAMPLE_SEQUENCE_LENGTH 						(Path_Window_Length+Times_Receive_One_Slot_Data*Chips_in_One_Buffer)//30720= 122880/4
#define SAMPLE_SEQUENCE_TAIL_LEN					(Path_Window_Length-16)
#define SAMPLE_SEQUENCE_TAIL_OFF					(SAMPLE_SEQUENCE_LENGTH-Path_Window_Length+16)


#define Times_Receive_One_Slot_Data_syn				18
#define Path_Window_Length_syn						576
#define SAMPLE_SEQUENCE_LENGTH_SYN 					(Path_Window_Length_syn+Times_Receive_One_Slot_Data_syn*Chips_in_One_Buffer)
#define SAMPLE_SEQUENCE_TAIL_OFF_SYN				(SAMPLE_SEQUENCE_LENGTH_SYN-Path_Window_Length_syn)
////////////////interface between FPGA and DSP/////////////////////
#define Start_Linkport_AD3              0x30052000
#define Stop_Linkport_AD3				0x30052002
#define Start_Linkport_AD1              0x30052004
#define Stop_Linkport_AD1				0x30052006
#define SS_IND_ADDRESS					0x3005201a
#define BS_IND_ADDRESS					0x30052018
#define LINKPORT_MODE					0x30051002
#define linkport_timing					0x30051000

#define pRead_Enable_clear			0x30004124
#define	pRead_End					0x30004126
#define	rpt_dsp3_watch_in_fpga		0x30040010
#define FPGA_Slot_no				0x30071000
#define Bts_sim_timing				0x30051014
//////////////////////internal interface define/////////////

#define	Interface_base_addr			0x140000
#define	Interface_end_addr			0x1403FF
#define	SYNC_dsp_reset				0
#define	SYNC_dsp_initial			1
#define	SYNC_AFC_init_value			4
#define	SYNC_AFC_up_bound			5
#define	SYNC_AFC_low_bound			6
#define	SYNC_AFC_step				7



//*************************************for track define******************************************
#define	TRK_TH					(50)
#define	FFT_size				(512)
#define	CP_LEN					(64)
#define	TRK_OFFSET				(32)


#define	Timing_forward_en			(0x30051010)
#define	Timing_backward_en			(0x30051012)




//************************************ Macros ************************************


///////////////////for stack////////////////////////
#define mPUSHQ(arg) \
  Q[k27 += -4] = arg;;

#define mPOPQ(arg) \
  k27 = k27 + 4;;  \
  arg = Q[k27 += 0];;

#define mENTER \
  j26 = j27 - 0x40; k26 = k27 - 0x40;; \
  [j27 += 0xFFFFFFF4] = cJMP; k27 = k27 - 0x04;;

#define mRETURN \
  cjmp = [j26 + 0x40];; \
  cjmp(ABS)(NP); j27:24 = Q[j26 + 0x44]; k27:24 = Q[k26 + 0x44];;



#endif	//for _SS_SYN_H_