uart.tan.summary

来自「自己用VHDL写的一个串口程序」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.747 ns
From           : START
To             : BEGINS:U0|TEMP[3]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.627 ns
From           : TRANSMIT:U1|XMIT_DONE
To             : XMIT_DONE
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.082 ns
From           : START
To             : BEGINS:U0|PRESENT_STATE.state3
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 199.52 MHz ( period = 5.012 ns )
From           : TRANSMIT:U1|TEMP[1]
To             : TRANSMIT:U1|TXD
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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