begins.vhd

自己用VHDL写的一个串口程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BEGINS IS
  PORT(BCLK: IN STD_LOGIC;
       VIN:  IN STD_LOGIC;
 XMIT_DONE: IN STD_LOGIC;
       VOUT: OUT STD_LOGIC
       );
END BEGINS;
 
ARCHITECTURE BEHAV OF BEGINS IS
TYPE STATE IS(STATE1,STATE2,STATE3);
SIGNAL PRESENT_STATE :STATE:=STATE1;
  BEGIN
    PROCESS(BCLK,VIN)
    VARIABLE TEMP: STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
     BEGIN
      IF BCLK'EVENT AND BCLK='1' THEN 
        CASE PRESENT_STATE IS
         WHEN STATE1 => IF VIN='1' THEN PRESENT_STATE <= STATE2;
						--ELSIF XMIT_DONE='1' THEN VOUT<='0';PRESENT_STATE <= STATE2;
                        ELSE PRESENT_STATE<= STATE1;
                        END IF;
         WHEN STATE2 => IF TEMP="1110" THEN PRESENT_STATE<=STATE3;VOUT<='1';
                        ELSIF VIN='1' THEN TEMP:=TEMP+1;
                        ELSE PRESENT_STATE<= STATE1;
                        END IF;
         WHEN STATE3 => VOUT<='0';
                        IF VIN='0' THEN PRESENT_STATE <= STATE1;TEMP:="0000";
						ELSIF XMIT_DONE='1' THEN VOUT<='0';PRESENT_STATE <= STATE2;
                        ELSE PRESENT_STATE <=STATE3;
                        END IF;
       END CASE;
     END IF;
    END PROCESS;
 END BEHAV;