uart.map.qmsg

来自「自己用VHDL写的一个串口程序」· QMSG 代码 · 共 23 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 14 10:52:18 2007 " "Info: Processing started: Mon May 14 10:52:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off UART -c UART " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off UART -c UART" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-RTL " "Info: Found design unit 1: fenpin-RTL" {  } { { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "E:/mywork/UART/fenpin.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UART.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file UART.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART-BEHAV " "Info: Found design unit 1: UART-BEHAV" {  } { { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 UART " "Info: Found entity 1: UART" {  } { { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BEGINS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file BEGINS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 BEGINS-BEHAV " "Info: Found design unit 1: BEGINS-BEHAV" {  } { { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 BEGINS " "Info: Found entity 1: BEGINS" {  } { { "BEGINS.vhd" "" { Text "E:/mywork/UART/BEGINS.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TRANSMIT.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TRANSMIT.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TRANSMIT-BEHAV " "Info: Found design unit 1: TRANSMIT-BEHAV" {  } { { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TRANSMIT " "Info: Found entity 1: TRANSMIT" {  } { { "TRANSMIT.vhd" "" { Text "E:/mywork/UART/TRANSMIT.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "UART " "Info: Elaborating entity \"UART\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "RESET UART.vhd(45) " "Warning (10540): VHDL Signal Declaration warning at UART.vhd(45): used explicit default value for signal \"RESET\" because signal was never assigned a value" {  } { { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 45 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0}
{ "Warning" "WVRFX_VHDL_USED_EXPLICIT_DEFAULT_VALUE" "DATAIN UART.vhd(46) " "Warning (10540): VHDL Signal Declaration warning at UART.vhd(46): used explicit default value for signal \"DATAIN\" because signal was never assigned a value" {  } { { "UART.vhd" "" { Text "E:/mywork/UART/UART.vhd" 46 0 0 } }  } 0 10540 "VHDL Signal Declaration warning at %2!s!: used explicit default value for signal \"%1!s!\" because signal was never assigned a value" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BEGINS BEGINS:U0 " "Info: Elaborating entity \"BEGINS\" for hierarchy \"BEGINS:U0\"" {  } { { "UART.vhd" "U0" { Text "E:/mywork/UART/UART.vhd" 51 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TRANSMIT TRANSMIT:U1 " "Info: Elaborating entity \"TRANSMIT\" for hierarchy \"TRANSMIT:U1\"" {  } { { "UART.vhd" "U1" { Text "E:/mywork/UART/UART.vhd" 52 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}