fenpin.vhd

自己用VHDL写的一个串口程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY fenpin IS
GENERIC (N:INTEGER :=5);
PORT(CLK:IN STD_LOGIC;
     CLKOUT:OUT STD_LOGIC);
END fenpin;


ARCHITECTURE RTL OF fenpin IS
SIGNAL COUNTER1:INTEGER RANGE 0 TO N-1;
SIGNAL COUNTER2:INTEGER RANGE 0 TO N-1;
SIGNAL COUNTER3:INTEGER RANGE 0 TO N-1;
SIGNAL CLK_REG1,CLK_REG2,CLK_REG3: STD_LOGIC;
signal celect	:std_logic;			--if N is even,celect is 1,else 0;

BEGIN

process(clk)
begin
	if (N mod 2 =0)then
		celect<='1';
	else
		celect<='0';
	end if;
end process;				--if N is even,celect is 1,else 0


PROCESS(CLK,celect)
BEGIN
	if (celect='1')then
		CLK_REG1<='0';
    elsif CLK'EVENT AND CLK='1' THEN
       IF COUNTER1=N-1 THEN
          COUNTER1<=0;
          CLK_REG1<=NOT CLK_REG1;
       ELSIF COUNTER1=(N-1)/2 THEN
          COUNTER1<=COUNTER1+1;
          CLK_REG1<=NOT CLK_REG1;
       ELSE
            COUNTER1<=COUNTER1+1;
       END IF;
    END IF;
END PROCESS;


PROCESS(CLK,celect)
BEGIN
	if (celect='1')then
		CLK_REG2<='0';
    elsif CLK'EVENT AND CLK='0' THEN
       IF COUNTER2=N-1 THEN
          COUNTER2<=0;
          CLK_REG2<=NOT CLK_REG2;
       ELSIF COUNTER2=(N-1)/2 THEN
          COUNTER2<=COUNTER2+1;
          CLK_REG2<=NOT CLK_REG2;
       ELSE
            COUNTER2<=COUNTER2+1;
       END IF;
    END IF;
END PROCESS;


process(clk,celect)
begin
	if (celect='1')then
	if (clk'event and clk='1')then
		if COUNTER3=N/2 THEN
		COUNTER3<=0;
		CLK_REG3<=NOT CLK_REG3;
		else
		COUNTER3<=COUNTER3+1;
		end if;
	end if;
	end if;
end process;


process(clk,celect,CLK_REG1,CLK_REG2,CLK_REG3)
begin
if(celect='1')then
CLKOUT<=CLK_REG3;
else
CLKOUT<=CLK_REG1 OR CLK_REG2;
end if;
end process;
END RTL;