uart.vhd

自己用VHDL写的一个串口程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY UART IS
GENERIC (N:INTEGER :=1042);--9600BAND:130; 			BAND=20000000/(16*2*2)
						   --2400BAND:521;
						   --1200BAND:1042;
						   --600BAND :2083;
--generic (N:INTEGER :=2 );--  这里必须注意，除以2就是4分频了！！！！band 是HZ的2倍关系 600 BAND=300 HZ
PORT(--DATAIN		:IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
     CLK		:IN  STD_LOGIC;
	 START 		:IN  STD_LOGIC;
     --RESET		:IN  STD_LOGIC;
  XMIT_DONE     :OUT STD_LOGIC;
	 TXD		:OUT STD_LOGIC;
	 CLKCESHI   :OUT STD_LOGIC
     );
END UART;

ARCHITECTURE BEHAV OF UART IS
COMPONENT BEGINS 
  PORT(BCLK: IN STD_LOGIC;
       VIN:  IN STD_LOGIC;
  XMIT_DONE: IN STD_LOGIC;
       VOUT: OUT STD_LOGIC
       );
END COMPONENT;

COMPONENT fenpin 
GENERIC (N:INTEGER );
PORT(CLK:IN STD_LOGIC;
     CLKOUT:OUT STD_LOGIC);
END COMPONENT;

COMPONENT TRANSMIT 
PORT(XBUF: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     BCLK: IN STD_LOGIC;
     RESETL:IN STD_LOGIC;
     XMIT_BEGIN: IN STD_LOGIC;
     TXD:    OUT STD_LOGIC;
     XMIT_DONE: OUT STD_LOGIC
     );
END COMPONENT;
--SIGNAL START  :STD_LOGIC:='1';
SIGNAL RESET  :STD_lOGIC:='0';
SIGNAL DATAIN :STD_LOGIC_VECTOR(7 DOWNTO 0):="01100000";
SIGNAL START_TRANS: STD_LOGIC;
SIGNAL CLKIN      : STD_LOGIC;
SIGNAL XMIT_DONEREG  : STD_LOGIC:='0';
BEGIN
U0:BEGINS PORT MAP(CLKIN,START,XMIT_DONEREG,START_TRANS);
U1:TRANSMIT PORT MAP(DATAIN,CLKIN,RESET,START_TRANS,TXD,XMIT_DONEREG);
U3:fenpin generic map(n)port map(CLK,CLKIN);
CLKCESHI<=CLKIN;
XMIT_DONE<=XMIT_DONEREG;
END BEHAV;