singt.fit.eqn

正弦波发生器

NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = GND;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L92;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L5);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[4] = NB1_q_b[7]_PORT_B_data_out[3];

--NB1_q_b[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[5] at M4K_X19_Y11
NB1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = GND;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L92;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L5);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[5] = NB1_q_b[7]_PORT_B_data_out[2];

--NB1_q_b[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[6] at M4K_X19_Y11
NB1_q_b[7]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = GND;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L92;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L5);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[6] = NB1_q_b[7]_PORT_B_data_out[1];


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y13_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y13_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y13_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y13_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);


--HB1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X24_Y11_N5
--operation mode is normal

HB1_Q[2] = AMPP_FUNCTION(A1L5, HB3_Q[2], HB8_Q[2], HB5_Q[0], !D1L2, D1L53);


--PB1L92 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1 at LC_X25_Y9_N2
--operation mode is normal

PB1L92 = AMPP_FUNCTION(HB1_Q[2]);

--PB1_ram_rom_incr_write_addr_reg is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg at LC_X25_Y9_N2
--operation mode is normal

PB1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L5, PB1_ram_rom_load_read_data, VCC, GND);


--F1_safe_q[0] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[0] at LC_X18_Y11_N1
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0] = DFFEA(F1_safe_q[0]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L41 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[0]~COUT0 at LC_X18_Y11_N1
--operation mode is arithmetic

F1L41_cout_0 = F1_safe_q[0];
F1L41 = CARRY(F1L41_cout_0);

--F1L51 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[0]~COUT1 at LC_X18_Y11_N1
--operation mode is arithmetic

F1L51_cout_1 = F1_safe_q[0];
F1L51 = CARRY(F1L51_cout_1);


--F1_safe_q[1] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[1] at LC_X18_Y11_N2
--operation mode is arithmetic

F1_safe_q[1]_lut_out = F1_safe_q[1] $ F1L41;
F1_safe_q[1] = DFFEA(F1_safe_q[1]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L71 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[1]~COUT0 at LC_X18_Y11_N2
--operation mode is arithmetic

F1L71_cout_0 = !F1L41 # !F1_safe_q[1];
F1L71 = CARRY(F1L71_cout_0);

--F1L81 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[1]~COUT1 at LC_X18_Y11_N2
--operation mode is arithmetic

F1L81_cout_1 = !F1L51 # !F1_safe_q[1];
F1L81 = CARRY(F1L81_cout_1);


--F1_safe_q[2] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[2] at LC_X18_Y11_N3
--operation mode is arithmetic

F1_safe_q[2]_lut_out = F1_safe_q[2] $ !F1L71;
F1_safe_q[2] = DFFEA(F1_safe_q[2]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L02 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[2]~COUT0 at LC_X18_Y11_N3
--operation mode is arithmetic

F1L02_cout_0 = F1_safe_q[2] & !F1L71;
F1L02 = CARRY(F1L02_cout_0);

--F1L12 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[2]~COUT1 at LC_X18_Y11_N3
--operation mode is arithmetic

F1L12_cout_1 = F1_safe_q[2] & !F1L81;
F1L12 = CARRY(F1L12_cout_1);


--F1_safe_q[3] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[3] at LC_X18_Y11_N4
--operation mode is arithmetic

F1_safe_q[3]_lut_out = F1_safe_q[3] $ F1L02;
F1_safe_q[3] = DFFEA(F1_safe_q[3]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L8 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|counter_cella3~COUT at LC_X18_Y11_N4
--operation mode is arithmetic

F1L8 = F1L32;


--F1_safe_q[4] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[4] at LC_X18_Y11_N5
--operation mode is arithmetic

F1_safe_q[4]_carry_eqn = (!F1L8 & GND) # (F1L8 & VCC);
F1_safe_q[4]_lut_out = F1_safe_q[4] $ !F1_safe_q[4]_carry_eqn;
F1_safe_q[4] = DFFEA(F1_safe_q[4]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L62 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[4]~COUT0 at LC_X18_Y11_N5
--operation mode is arithmetic

F1L62_cout_0 = F1_safe_q[4] & !F1L8;
F1L62 = CARRY(F1L62_cout_0);

--F1L72 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[4]~COUT1 at LC_X18_Y11_N5
--operation mode is arithmetic

F1L72_cout_1 = F1_safe_q[4] & !F1L8;
F1L72 = CARRY(F1L72_cout_1);


--F1_safe_q[5] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[5] at LC_X18_Y11_N6
--operation mode is normal

F1_safe_q[5]_carry_eqn = (!F1L8 & F1L62) # (F1L8 & F1L72);
F1_safe_q[5]_lut_out = F1_safe_q[5]_carry_eqn $ F1_safe_q[5];
F1_safe_q[5] = DFFEA(F1_safe_q[5]_lut_out, GLOBAL(CLK), VCC, , , , );


--PB1_ram_rom_data_reg[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X23_Y11_N0
--operation mode is normal

PB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, altera_internal_jtag, PB1L01, NB1_q_b[7], PB1_ram_rom_data_reg[7], VCC, PB1L9);


--QB1_safe_q[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[0] at LC_X26_Y11_N1
--operation mode is arithmetic

QB1_safe_q[0] = AMPP_FUNCTION(A1L5, QB1_safe_q[0], PB1L31, !HB1_Q[0], PB1_ram_rom_incr_addr);

--QB1L41 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[0]~COUT0 at LC_X26_Y11_N1
--operation mode is arithmetic

QB1L41 = AMPP_FUNCTION(QB1_safe_q[0]);

--QB1L51 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[0]~COUT1 at LC_X26_Y11_N1
--operation mode is arithmetic

QB1L51 = AMPP_FUNCTION(QB1_safe_q[0]);


--QB1_safe_q[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[1] at LC_X26_Y11_N2
--operation mode is arithmetic

QB1_safe_q[1] = AMPP_FUNCTION(A1L5, QB1_safe_q[1], PB1L41, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L41, QB1L51);

--QB1L71 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[1]~COUT0 at LC_X26_Y11_N2
--operation mode is arithmetic

QB1L71 = AMPP_FUNCTION(QB1_safe_q[1], QB1L41);

--QB1L81 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[1]~COUT1 at LC_X26_Y11_N2
--operation mode is arithmetic

QB1L81 = AMPP_FUNCTION(QB1_safe_q[1], QB1L51);


--QB1_safe_q[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[2] at LC_X26_Y11_N3
--operation mode is arithmetic

QB1_safe_q[2] = AMPP_FUNCTION(A1L5, QB1_safe_q[2], PB1L51, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L71, QB1L81);

--QB1L02 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[2]~COUT0 at LC_X26_Y11_N3
--operation mode is arithmetic

QB1L02 = AMPP_FUNCTION(QB1_safe_q[2], QB1L71);

--QB1L12 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[2]~COUT1 at LC_X26_Y11_N3
--operation mode is arithmetic

QB1L12 = AMPP_FUNCTION(QB1_safe_q[2], QB1L81);


--QB1_safe_q[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[3] at LC_X26_Y11_N4
--operation mode is arithmetic

QB1_safe_q[3] = AMPP_FUNCTION(A1L5, QB1_safe_q[3], PB1L61, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L02, QB1L12);

--QB1L8 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|counter_cella3~COUT at LC_X26_Y11_N4
--operation mode is arithmetic

QB1L8 = AMPP_FUNCTION(QB1_safe_q[3], QB1L02, QB1L12);


--QB1_safe_q[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[4] at LC_X26_Y11_N5
--operation mode is arithmetic

QB1_safe_q[4] = AMPP_FUNCTION(A1L5, QB1_safe_q[4], PB1L71, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L8);