singt.tan.qmsg

正弦波发生器

{ "Info" "ITDB_TH_RESULT" "sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] altera_internal_jtag altera_internal_jtag~TCKUTAP 2.839 ns register " "Info: th for register sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] (data pin = altera_internal_jtag, clock pin = altera_internal_jtag~TCKUTAP) is 2.839 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.042 ns + Longest register " "Info: + Longest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 5.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 254 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 254; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.331 ns) + CELL(0.711 ns) 5.042 ns sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 2 REG LC_X23_Y13_N8 1 " "Info: 2: + IC(4.331 ns) + CELL(0.711 ns) = 5.042 ns; Loc. = LC_X23_Y13_N8; Fanout = 1; REG Node = 'sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "5.042 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.10 % " "Info: Total cell delay = 0.711 ns ( 14.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.331 ns 85.90 % " "Info: Total interconnect delay = 4.331 ns ( 85.90 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "5.042 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.218 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.218 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y13_N1 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 14; PIN Node = 'altera_internal_jtag'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "" { altera_internal_jtag } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.103 ns) + CELL(0.115 ns) 2.218 ns sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] 2 REG LC_X23_Y13_N8 1 " "Info: 2: + IC(2.103 ns) + CELL(0.115 ns) = 2.218 ns; Loc. = LC_X23_Y13_N8; Fanout = 1; REG Node = 'sld_signaltap:sinout\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "2.218 ns" { altera_internal_jtag sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 59 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 5.18 % " "Info: Total cell delay = 0.115 ns ( 5.18 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.103 ns 94.82 % " "Info: Total interconnect delay = 2.103 ns ( 94.82 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "2.218 ns" { altera_internal_jtag sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "5.042 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "2.218 ns" { altera_internal_jtag sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK DOUT\[1\] data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a7~porta_address_reg5 13.301 ns memory " "Info: Minimum tco from clock CLK to destination pin DOUT\[1\] through memory data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a7~porta_address_reg5 is 13.301 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.158 ns + Shortest memory " "Info: + Shortest clock path from clock CLK to source memory is 3.158 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 149 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 149; CLK Node = 'CLK'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "" { CLK } "NODE_NAME" } } } { "E:/highflu documents/quartwork/singt/singt.vhd" "" "" { Text "E:/highflu documents/quartwork/singt/singt.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.722 ns) 3.158 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a7~porta_address_reg5 2 MEM M4K_X19_Y11 8 " "Info: 2: + IC(0.967 ns) + CELL(0.722 ns) = 3.158 ns; Loc. = M4K_X19_Y11; Fanout = 8; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a7~porta_address_reg5'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "1.689 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg5 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" "" "" { Text "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" 267 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 69.38 % " "Info: Total cell delay = 2.191 ns ( 69.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.967 ns 30.62 % " "Info: Total interconnect delay = 0.967 ns ( 30.62 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "3.158 ns" { CLK data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg5 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" "" "" { Text "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" 267 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.493 ns + Shortest memory pin " "Info: + Shortest memory to pin delay is 9.493 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a7~porta_address_reg5 1 MEM M4K_X19_Y11 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y11; Fanout = 8; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|ram_block3a7~porta_address_reg5'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg5 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" "" "" { Text "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" 267 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|q_a\[1\] 2 MEM M4K_X19_Y11 2 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X19_Y11; Fanout = 2; MEM Node = 'data_rom:u1\|altsyncram:altsyncram_component\|altsyncram_hat:auto_generated\|altsyncram_71b2:altsyncram1\|q_a\[1\]'" {  } { { "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/singt/db/singt_cmp.qrpt" Compiler "singt" "UNKNOWN" "V1" "E:/highflu documents/quartwork/singt/db/singt.quartus_db" { Floorplan "" "" "4.308 ns" { data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg5 data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" "" "" { Text "E:/highflu documents/quartwork/singt/db/altsyncram_71b2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_N