singt.map.eqn

正弦波发生器

NB1_q_b[1]_PORT_B_write_enable_reg = DFFE(NB1_q_b[1]_PORT_B_write_enable, NB1_q_b[1]_clock_1, , , );
NB1_q_b[1]_clock_0 = CLK;
NB1_q_b[1]_clock_1 = A1L5;
NB1_q_b[1]_PORT_B_data_out = MEMORY(NB1_q_b[1]_PORT_A_data_in_reg, NB1_q_b[1]_PORT_B_data_in_reg, NB1_q_b[1]_PORT_A_address_reg, NB1_q_b[1]_PORT_B_address_reg, NB1_q_b[1]_PORT_A_write_enable_reg, NB1_q_b[1]_PORT_B_write_enable_reg, , , NB1_q_b[1]_clock_0, NB1_q_b[1]_clock_1, , , , );
NB1_q_b[1] = NB1_q_b[1]_PORT_B_data_out[0];


--NB1_q_a[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 64, Port A Width: 1, Port B Depth: 64, Port B Width: 1
--Port A Logical Depth: 64, Port A Logical Width: 8, Port B Logical Depth: 64, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[0]_PORT_A_data_in = VCC;
NB1_q_a[0]_PORT_A_data_in_reg = DFFE(NB1_q_a[0]_PORT_A_data_in, NB1_q_a[0]_clock_0, , , );
NB1_q_a[0]_PORT_B_data_in = PB1_ram_rom_data_reg[0];
NB1_q_a[0]_PORT_B_data_in_reg = DFFE(NB1_q_a[0]_PORT_B_data_in, NB1_q_a[0]_clock_1, , , );
NB1_q_a[0]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_a[0]_PORT_A_address_reg = DFFE(NB1_q_a[0]_PORT_A_address, NB1_q_a[0]_clock_0, , , );
NB1_q_a[0]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_a[0]_PORT_B_address_reg = DFFE(NB1_q_a[0]_PORT_B_address, NB1_q_a[0]_clock_1, , , );
NB1_q_a[0]_PORT_A_write_enable = GND;
NB1_q_a[0]_PORT_A_write_enable_reg = DFFE(NB1_q_a[0]_PORT_A_write_enable, NB1_q_a[0]_clock_0, , , );
NB1_q_a[0]_PORT_B_write_enable = PB1L92;
NB1_q_a[0]_PORT_B_write_enable_reg = DFFE(NB1_q_a[0]_PORT_B_write_enable, NB1_q_a[0]_clock_1, , , );
NB1_q_a[0]_clock_0 = CLK;
NB1_q_a[0]_clock_1 = A1L5;
NB1_q_a[0]_PORT_A_data_out = MEMORY(NB1_q_a[0]_PORT_A_data_in_reg, NB1_q_a[0]_PORT_B_data_in_reg, NB1_q_a[0]_PORT_A_address_reg, NB1_q_a[0]_PORT_B_address_reg, NB1_q_a[0]_PORT_A_write_enable_reg, NB1_q_a[0]_PORT_B_write_enable_reg, , , NB1_q_a[0]_clock_0, NB1_q_a[0]_clock_1, , , , );
NB1_q_a[0] = NB1_q_a[0]_PORT_A_data_out[0];

--NB1_q_b[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|q_b[0]
NB1_q_b[0]_PORT_A_data_in = VCC;
NB1_q_b[0]_PORT_A_data_in_reg = DFFE(NB1_q_b[0]_PORT_A_data_in, NB1_q_b[0]_clock_0, , , );
NB1_q_b[0]_PORT_B_data_in = PB1_ram_rom_data_reg[0];
NB1_q_b[0]_PORT_B_data_in_reg = DFFE(NB1_q_b[0]_PORT_B_data_in, NB1_q_b[0]_clock_1, , , );
NB1_q_b[0]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5]);
NB1_q_b[0]_PORT_A_address_reg = DFFE(NB1_q_b[0]_PORT_A_address, NB1_q_b[0]_clock_0, , , );
NB1_q_b[0]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5]);
NB1_q_b[0]_PORT_B_address_reg = DFFE(NB1_q_b[0]_PORT_B_address, NB1_q_b[0]_clock_1, , , );
NB1_q_b[0]_PORT_A_write_enable = GND;
NB1_q_b[0]_PORT_A_write_enable_reg = DFFE(NB1_q_b[0]_PORT_A_write_enable, NB1_q_b[0]_clock_0, , , );
NB1_q_b[0]_PORT_B_write_enable = PB1L92;
NB1_q_b[0]_PORT_B_write_enable_reg = DFFE(NB1_q_b[0]_PORT_B_write_enable, NB1_q_b[0]_clock_1, , , );
NB1_q_b[0]_clock_0 = CLK;
NB1_q_b[0]_clock_1 = A1L5;
NB1_q_b[0]_PORT_B_data_out = MEMORY(NB1_q_b[0]_PORT_A_data_in_reg, NB1_q_b[0]_PORT_B_data_in_reg, NB1_q_b[0]_PORT_A_address_reg, NB1_q_b[0]_PORT_B_address_reg, NB1_q_b[0]_PORT_A_write_enable_reg, NB1_q_b[0]_PORT_B_write_enable_reg, , , NB1_q_b[0]_clock_0, NB1_q_b[0]_clock_1, , , , );
NB1_q_b[0] = NB1_q_b[0]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L22Q);


--PB1_ram_rom_incr_write_addr_reg is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg
--operation mode is normal

PB1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L5, PB1_ram_rom_load_read_data, VCC);


--HB1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

HB1_Q[2] = AMPP_FUNCTION(A1L5, HB3_Q[2], HB8_Q[2], HB5_Q[0], !D1L2, D1L53);


--PB1L92 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1
--operation mode is normal

PB1L92 = AMPP_FUNCTION(PB1_ram_rom_incr_write_addr_reg, HB1_Q[2]);


--F1_safe_q[0] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[0]
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0] = DFFEA(F1_safe_q[0]_lut_out, CLK, VCC, , , , );

--F1L2 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

F1L2 = CARRY(F1_safe_q[0]);


--F1_safe_q[1] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[1]
--operation mode is arithmetic

F1_safe_q[1]_carry_eqn = F1L2;
F1_safe_q[1]_lut_out = F1_safe_q[1] $ F1_safe_q[1]_carry_eqn;
F1_safe_q[1] = DFFEA(F1_safe_q[1]_lut_out, CLK, VCC, , , , );

--F1L4 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

F1L4 = CARRY(!F1L2 # !F1_safe_q[1]);


--F1_safe_q[2] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[2]
--operation mode is arithmetic

F1_safe_q[2]_carry_eqn = F1L4;
F1_safe_q[2]_lut_out = F1_safe_q[2] $ !F1_safe_q[2]_carry_eqn;
F1_safe_q[2] = DFFEA(F1_safe_q[2]_lut_out, CLK, VCC, , , , );

--F1L6 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

F1L6 = CARRY(F1_safe_q[2] & !F1L4);


--F1_safe_q[3] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[3]
--operation mode is arithmetic

F1_safe_q[3]_carry_eqn = F1L6;
F1_safe_q[3]_lut_out = F1_safe_q[3] $ F1_safe_q[3]_carry_eqn;
F1_safe_q[3] = DFFEA(F1_safe_q[3]_lut_out, CLK, VCC, , , , );

--F1L8 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

F1L8 = CARRY(!F1L6 # !F1_safe_q[3]);


--F1_safe_q[4] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[4]
--operation mode is arithmetic

F1_safe_q[4]_carry_eqn = F1L8;
F1_safe_q[4]_lut_out = F1_safe_q[4] $ !F1_safe_q[4]_carry_eqn;
F1_safe_q[4] = DFFEA(F1_safe_q[4]_lut_out, CLK, VCC, , , , );

--F1L01 is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

F1L01 = CARRY(F1_safe_q[4] & !F1L8);


--F1_safe_q[5] is lpm_counter:Q1_rtl_0|cntr_es6:auto_generated|safe_q[5]
--operation mode is normal

F1_safe_q[5]_carry_eqn = F1L01;
F1_safe_q[5]_lut_out = F1_safe_q[5] $ F1_safe_q[5]_carry_eqn;
F1_safe_q[5] = DFFEA(F1_safe_q[5]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[7] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

PB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[7], altera_internal_jtag, NB1_q_b[7], PB1L01, VCC, PB1L9);


--QB1_safe_q[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[0]
--operation mode is arithmetic

QB1_safe_q[0] = AMPP_FUNCTION(A1L5, QB1_safe_q[0], PB1L31, !HB1_Q[0], PB1_ram_rom_incr_addr);

--QB1L2 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

QB1L2 = AMPP_FUNCTION(QB1_safe_q[0]);


--QB1_safe_q[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[1]
--operation mode is arithmetic

QB1_safe_q[1] = AMPP_FUNCTION(A1L5, QB1_safe_q[1], PB1L41, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L2);

--QB1L4 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

QB1L4 = AMPP_FUNCTION(QB1_safe_q[1], QB1L2);


--QB1_safe_q[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[2]
--operation mode is arithmetic

QB1_safe_q[2] = AMPP_FUNCTION(A1L5, QB1_safe_q[2], PB1L51, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L4);

--QB1L6 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

QB1L6 = AMPP_FUNCTION(QB1_safe_q[2], QB1L4);


--QB1_safe_q[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[3]
--operation mode is arithmetic

QB1_safe_q[3] = AMPP_FUNCTION(A1L5, QB1_safe_q[3], PB1L61, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L6);

--QB1L8 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

QB1L8 = AMPP_FUNCTION(QB1_safe_q[3], QB1L6);


--QB1_safe_q[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[4]
--operation mode is arithmetic

QB1_safe_q[4] = AMPP_FUNCTION(A1L5, QB1_safe_q[4], PB1L71, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L8);

--QB1L01 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

QB1L01 = AMPP_FUNCTION(QB1_safe_q[4], QB1L8);


--QB1_safe_q[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_t98:auto_generated|safe_q[5]
--operation mode is normal

QB1_safe_q[5] = AMPP_FUNCTION(A1L5, QB1_safe_q[5], PB1L81, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01);


--PB1_ram_rom_data_reg[6] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

PB1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[7], NB1_q_b[6], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[5] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

PB1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[6], NB1_q_b[5], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[4] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

PB1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[5], NB1_q_b[4], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

PB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[3], PB1_ram_rom_data_reg[4], NB1_q_b[3], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[2] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal

PB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[3], NB1_q_b[2], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

PB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[2], NB1_q_b[1], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[0] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

PB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, PB1_ram_rom_data_reg[0], PB1_ram_rom_data_reg[1], NB1_q_b[0], PB1L01, VCC, PB1L9);


--D1L22Q is sld_hub:sld_hub_inst|HUB_TDO~reg0
--operation mode is normal

D1L22Q = AMPP_FUNCTION(!A1L5, D1L81, D1L91, D1_jtag_debug_mode_usr1, D1L12, !KB1_state[8], D1L84);


--RB1_safe_q[3] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[3]
--operation mode is normal

RB1_safe_q[3] = AMPP_FUNCTION(A1L5, RB1_safe_q[3], PB1L01, !HB1_Q[3], PB1_ram_rom_load_read_data, RB1L6);


--RB1_safe_q[1] is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]
--operation mode is arithmetic

RB1_safe_q[1] = AMPP_FUNCTION(A1L5, RB1_safe_q[1], PB1L01, !HB1_Q[3], PB1_ram_rom_load_read_data, RB1L2);

--RB1L4 is data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic