singt.tan.rpt

正弦波发生器

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                    ; To                                                                                                                            ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 0.645 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                                                            ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]                                                                                   ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 15.313 ns                        ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg5                                   ; DOUT[6]                                                                                                                       ; CLK                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                ; altera_reserved_tdo                                                                                                           ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 2.839 ns                         ; altera_internal_jtag                                                                                                                                                    ; sld_signaltap:sinout|sld_rom_sr:crc_rom_sr|WORD_SR[3]                                                                         ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 13.301 ns                        ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg5                                   ; DOUT[1]                                                                                                                       ; CLK                          ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                ; altera_reserved_tdo                                                                                                           ;                              ;                              ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 113.61 MHz ( period = 8.802 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                                                      ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                             ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 143.06 MHz ( period = 6.990 ns ) ; sld_signaltap:sinout|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1] ; sld_signaltap:sinout|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_6g82:auto_generated|ram_block1a0~porta_we_reg ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                         ;                                                                                                                               ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                  ; To                                                                                                                                                                                                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 143.06 MHz ( period = 6.990 ns )                    ; sld_signaltap:sinout|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_nt9:auto_generated|safe_q[1]                                                                               ; sld_signaltap:sinout|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_6g82:auto_generated|ram_block1a0~porta_we_reg                                                                                 ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 144.40 MHz ( period = 6.925 ns )                    ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg0                                                                                                                 ; sld_signaltap:sinout|acq_trigger_in_reg[7]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 144.40 MHz ( period = 6.925 ns )                    ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg1                                                                                                                 ; sld_signaltap:sinout|acq_trigger_in_reg[7]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 144.40 MHz ( period = 6.925 ns )                    ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg2                                                                                                                 ; sld_signaltap:sinout|acq_trigger_in_reg[7]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 144.40 MHz ( period = 6.925 ns )                    ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg3                                                                                                                 ; sld_signaltap:sinout|acq_trigger_in_reg[7]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 144.40 MHz ( period = 6.925 ns )                    ; data_rom:u1|altsyncram:altsyncram_component|altsyncram_hat:auto_generated|altsyncram_71b2:altsyncram1|ram_block3a7~porta_address_reg4                                                                                                                 ; sld_signaltap:sinout|acq_trigger_in_reg[7]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;