song.tan.rpt

用VHDL演示MUSIC的程序

+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C12Q240C8       ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                           ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                ; To                                                                                         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 18.359 ns                        ; speakera:u3|\delayspks:count2                                                                                       ; spkout                                                                                     ; clk12mhz   ;          ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 12.260 ns                        ; notetabs:u1|music:u4|altsyncram:altsyncram_component|altsyncram_v821:auto_generated|q_a[0]                          ; code1[1]                                                                                   ; clk8hz     ;          ; 0            ;
; Clock Setup: 'clk12mhz'      ; N/A   ; None          ; 184.64 MHz ( period = 5.416 ns ) ; speakera:u3|lpm_counter:\genspks:count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[2]                                 ; speakera:u3|lpm_counter:\genspks:count11[0]_rtl_0|cntr_7t7:auto_generated|safe_q[0]        ; clk12mhz   ; clk12mhz ; 0            ;
; Clock Setup: 'clk8hz'        ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns ) ; notetabs:u1|music:u4|altsyncram:altsyncram_component|altsyncram_v821:auto_generated|ram_block1a0~porta_address_reg7 ; notetabs:u1|music:u4|altsyncram:altsyncram_component|altsyncram_v821:auto_generated|q_a[0] ; clk8hz     ; clk8hz   ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                                     ;                                                                                            ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk8hz          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; clk12mhz        ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk8hz'                                                                                                                                                                                                                                                                                                                                                                                          ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                                ; To                                                                                                                  ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; notetabs:u1|music:u4|altsyncram:altsyncram_component|altsyncram_v821:auto_generated|ram_block1a0~porta_datain_reg3  ; notetabs:u1|music:u4|altsyncram:altsyncram_component|altsyncram_v821:auto_generated|ram_block1a0~porta_memory_reg3  ; clk8hz     ; clk8hz   ; None                        ; None                      ; None                    ;