adcdac.map.summary

来自「简易示波器的VHDL程序」· SUMMARY 代码 · 共 12 行

Flow Status : Successful - Tue Oct 23 19:16:20 2007
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : adcdac
Top-level Entity Name : adcdac
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Production
Total logic elements : 16
Total pins : 19
Total memory bits : 0
Total PLLs : 0