adcdac.map.qmsg

简易示波器的VHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 23 19:16:16 2007 " "Info: Processing started: Tue Oct 23 19:16:16 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off adcdac -c adcdac " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off adcdac -c adcdac" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adcdac.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adcdac.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adcdac-behave_adcdac " "Info: Found design unit 1: adcdac-behave_adcdac" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "adcdac-behave_adcdac" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 adcdac " "Info: Found entity 1: adcdac" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "adcdac" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cqi\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: cqi\[0\]~0" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "cqi\[0\]~0" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_uu7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_uu7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_uu7 " "Info: Found entity 1: cntr_uu7" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "cntr_uu7" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "35 " "Info: Implemented 35 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 23 19:16:20 2007 " "Info: Processing ended: Tue Oct 23 19:16:20 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}