adcdac.tan.qmsg

简易示波器的VHDL程序

{ "Info" "ITDB_FULL_TPD_RESULT" "lm311 dispdata\[0\] 9.912 ns Shortest " "Info: Shortest tpd from source pin lm311 to destination pin dispdata\[0\] is 9.912 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns lm311 1 PIN PIN_158 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lm311 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.117 ns) + CELL(0.114 ns) 6.700 ns dispdata~15 2 COMB LC_X52_Y20_N8 1 " "Info: 2: + IC(5.117 ns) + CELL(0.114 ns) = 6.700 ns; Loc. = LC_X52_Y20_N8; Fanout = 1; COMB Node = 'dispdata~15'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "5.231 ns" { lm311 dispdata~15 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(2.124 ns) 9.912 ns dispdata\[0\] 3 PIN PIN_161 0 " "Info: 3: + IC(1.088 ns) + CELL(2.124 ns) = 9.912 ns; Loc. = PIN_161; Fanout = 0; PIN Node = 'dispdata\[0\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.212 ns" { dispdata~15 dispdata[0] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.707 ns 37.40 % " "Info: Total cell delay = 3.707 ns ( 37.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.205 ns 62.60 % " "Info: Total interconnect delay = 6.205 ns ( 62.60 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "9.912 ns" { lm311 dispdata~15 dispdata[0] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 23 19:16:38 2007 " "Info: Processing ended: Tue Oct 23 19:16:38 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}