adcdac.tan.qmsg

简易示波器的VHDL程序

{ "Info" "ITDB_TSU_RESULT" "lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] lm311 clk 4.336 ns register " "Info: tsu for register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] (data pin = lm311, clock pin = clk) is 4.336 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.460 ns + Longest pin register " "Info: + Longest pin to register delay is 7.460 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns lm311 1 PIN PIN_158 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lm311 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.124 ns) + CELL(0.867 ns) 7.460 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] 2 REG LC_X52_Y20_N7 3 " "Info: 2: + IC(5.124 ns) + CELL(0.867 ns) = 7.460 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "5.991 ns" { lm311 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 31.31 % " "Info: Total cell delay = 2.336 ns ( 31.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.124 ns 68.69 % " "Info: Total interconnect delay = 5.124 ns ( 68.69 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "7.460 ns" { lm311 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.161 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.711 ns) 3.161 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] 2 REG LC_X52_Y20_N7 3 " "Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.692 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.97 % " "Info: Total cell delay = 2.180 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns 31.03 % " "Info: Total interconnect delay = 0.981 ns ( 31.03 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "7.460 ns" { lm311 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dd\[1\] lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] 12.761 ns register " "Info: tco from clock clk to destination pin dd\[1\] through register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] is 12.761 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.161 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.711 ns) 3.161 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] 2 REG LC_X52_Y20_N1 5 " "Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.692 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.97 % " "Info: Total cell delay = 2.180 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns 31.03 % " "Info: Total interconnect delay = 0.981 ns ( 31.03 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.376 ns + Longest register pin " "Info: + Longest register to pin delay is 9.376 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] 1 REG LC_X52_Y20_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.252 ns) + CELL(2.124 ns) 9.376 ns dd\[1\] 2 PIN PIN_41 0 " "Info: 2: + IC(7.252 ns) + CELL(2.124 ns) = 9.376 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'dd\[1\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "9.376 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] dd[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 22.65 % " "Info: Total cell delay = 2.124 ns ( 22.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.252 ns 77.35 % " "Info: Total interconnect delay = 7.252 ns ( 77.35 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "9.376 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] dd[1] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "9.376 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] dd[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "lm311 dispdata\[6\] 10.475 ns Longest " "Info: Longest tpd from source pin lm311 to destination pin dispdata\[6\] is 10.475 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns lm311 1 PIN PIN_158 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lm311 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.236 ns) + CELL(0.114 ns) 6.819 ns dispdata~9 2 COMB LC_X52_Y21_N6 1 " "Info: 2: + IC(5.236 ns) + CELL(0.114 ns) = 6.819 ns; Loc. = LC_X52_Y21_N6; Fanout = 1; COMB Node = 'dispdata~9'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "5.350 ns" { lm311 dispdata~9 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.532 ns) + CELL(2.124 ns) 10.475 ns dispdata\[6\] 3 PIN PIN_167 0 " "Info: 3: + IC(1.532 ns) + CELL(2.124 ns) = 10.475 ns; Loc. = PIN_167; Fanout = 0; PIN Node = 'dispdata\[6\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.656 ns" { dispdata~9 dispdata[6] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.707 ns 35.39 % " "Info: Total cell delay = 3.707 ns ( 35.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.768 ns 64.61 % " "Info: Total interconnect delay = 6.768 ns ( 64.61 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "10.475 ns" { lm311 dispdata~9 dispdata[6] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] lm311 clk -4.284 ns register " "Info: th for register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] (data pin = lm311, clock pin = clk) is -4.284 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.161 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.711 ns) 3.161 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] 2 REG LC_X52_Y20_N7 3 " "Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.692 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.97 % " "Info: Total cell delay = 2.180 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns 31.03 % " "Info: Total interconnect delay = 0.981 ns ( 31.03 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.460 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.460 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns lm311 1 PIN PIN_158 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lm311 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.124 ns) + CELL(0.867 ns) 7.460 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] 2 REG LC_X52_Y20_N7 3 " "Info: 2: + IC(5.124 ns) + CELL(0.867 ns) = 7.460 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "5.991 ns" { lm311 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 31.31 % " "Info: Total cell delay = 2.336 ns ( 31.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.124 ns 68.69 % " "Info: Total interconnect delay = 5.124 ns ( 68.69 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "7.460 ns" { lm311 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "7.460 ns" { lm311 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk dispdata\[0\] lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\] 7.568 ns register " "Info: Minimum tco from clock clk to destination pin dispdata\[0\] through register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\] is 7.568 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.161 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.711 ns) 3.161 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\] 2 REG LC_X52_Y20_N0 5 " "Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N0; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.692 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.97 % " "Info: Total cell delay = 2.180 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns 31.03 % " "Info: Total interconnect delay = 0.981 ns ( 31.03 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.183 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.183 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\] 1 REG LC_X52_Y20_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y20_N0; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.442 ns) 0.971 ns dispdata~15 2 COMB LC_X52_Y20_N8 1 " "Info: 2: + IC(0.529 ns) + CELL(0.442 ns) = 0.971 ns; Loc. = LC_X52_Y20_N8; Fanout = 1; COMB Node = 'dispdata~15'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.971 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] dispdata~15 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(2.124 ns) 4.183 ns dispdata\[0\] 3 PIN PIN_161 0 " "Info: 3: + IC(1.088 ns) + CELL(2.124 ns) = 4.183 ns; Loc. = PIN_161; Fanout = 0; PIN Node = 'dispdata\[0\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.212 ns" { dispdata~15 dispdata[0] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.566 ns 61.34 % " "Info: Total cell delay = 2.566 ns ( 61.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.617 ns 38.66 % " "Info: Total interconnect delay = 1.617 ns ( 38.66 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "4.183 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] dispdata~15 dispdata[0] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "4.183 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] dispdata~15 dispdata[0] } "NODE_NAME" } } }  } 0}