adcdac.tan.qmsg

简易示波器的VHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 23 19:16:37 2007 " "Info: Processing started: Tue Oct 23 19:16:37 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off adcdac -c adcdac --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off adcdac -c adcdac --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[5\] 275.03 MHz Internal " "Info: Clock clk Internal fmax is restricted to 275.03 MHz between source register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] and destination register lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[5\]" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.266 ns + Longest register register " "Info: + Longest register to register delay is 2.266 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] 1 REG LC_X52_Y20_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]~COUT0 2 COMB LC_X52_Y20_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X52_Y20_N1; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]~COUT0'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.093 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT0 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[2\]~COUT0 3 COMB LC_X52_Y20_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X52_Y20_N2; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[2\]~COUT0'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.078 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT0 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[3\]~COUT0 4 COMB LC_X52_Y20_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X52_Y20_N3; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[3\]~COUT0'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.078 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT0 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|counter_cella4~COUT 5 COMB LC_X52_Y20_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X52_Y20_N4; Fanout = 3; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|counter_cella4~COUT'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.178 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 71 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.266 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[5\] 6 REG LC_X52_Y20_N5 5 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X52_Y20_N5; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[5\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.839 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns 76.65 % " "Info: Total cell delay = 1.737 ns ( 76.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns 23.35 % " "Info: Total interconnect delay = 0.529 ns ( 23.35 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "2.266 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.161 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.711 ns) 3.161 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[5\] 2 REG LC_X52_Y20_N5 5 " "Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N5; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[5\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.692 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.97 % " "Info: Total cell delay = 2.180 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns 31.03 % " "Info: Total interconnect delay = 0.981 ns ( 31.03 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.161 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.161 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.981 ns) + CELL(0.711 ns) 3.161 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\] 2 REG LC_X52_Y20_N1 5 " "Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "1.692 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 68.97 % " "Info: Total cell delay = 2.180 ns ( 68.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.981 ns 31.03 % " "Info: Total interconnect delay = 0.981 ns ( 31.03 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "2.266 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT0 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "3.161 ns" { clk lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0}