adcdac.fit.qmsg

简易示波器的VHDL程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 23 19:16:23 2007 " "Info: Processing started: Tue Oct 23 19:16:23 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off adcdac -c adcdac " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off adcdac -c adcdac" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "adcdac EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design adcdac" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 28 " "Info: Automatically promoted signal clk to use Global clock in PIN 28" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 6 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clr Global clock " "Info: Automatically promoted signal clr to use Global clock" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clr " "Info: Pin clr drives global clock, but is not placed in a dedicated clock pin position" {  } { { "E:/highflu documents/quartwork/adcdac/adcdac.vhd" "" "" { Text "E:/highflu documents/quartwork/adcdac/adcdac.vhd" 8 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clr" } } } } { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { clr } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/adcdac.fld" "" "" { Floorplan "E:/highflu documents/quartwork/adcdac/adcdac.fld" "" "" { clr } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.354 ns register register " "Info: Estimated most critical path is register to register delay of 2.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\] 1 REG LAB_X52_Y20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X52_Y20; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.575 ns) 0.958 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\]~COUT1 2 COMB LAB_X52_Y20 2 " "Info: 2: + IC(0.383 ns) + CELL(0.575 ns) = 0.958 ns; Loc. = LAB_X52_Y20; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[0\]~COUT1'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.958 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]~COUT1 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.038 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]~COUT1 3 COMB LAB_X52_Y20 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.038 ns; Loc. = LAB_X52_Y20; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[1\]~COUT1'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.080 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT1 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.118 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[2\]~COUT1 4 COMB LAB_X52_Y20 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.118 ns; Loc. = LAB_X52_Y20; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[2\]~COUT1'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.080 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT1 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.198 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[3\]~COUT1 5 COMB LAB_X52_Y20 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.198 ns; Loc. = LAB_X52_Y20; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[3\]~COUT1'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.080 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT1 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.456 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|counter_cella4~COUT 6 COMB LAB_X52_Y20 3 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.456 ns; Loc. = LAB_X52_Y20; Fanout = 3; COMB Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|counter_cella4~COUT'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.258 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 71 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.354 ns lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\] 7 REG LAB_X52_Y20 3 " "Info: 7: + IC(0.000 ns) + CELL(0.898 ns) = 2.354 ns; Loc. = LAB_X52_Y20; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0\|cntr_uu7:auto_generated\|safe_q\[7\]'" {  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "0.898 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" "" "" { Text "E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf" 108 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.971 ns 83.73 % " "Info: Total cell delay = 1.971 ns ( 83.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.383 ns 16.27 % " "Info: Total interconnect delay = 0.383 ns ( 16.27 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/adcdac/db/adcdac_cmp.qrpt" Compiler "adcdac" "UNKNOWN" "V1" "E:/highflu documents/quartwork/adcdac/db/adcdac.quartus_db" { Floorplan "" "" "2.354 ns" { lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT1 lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "0 " "Info: Fitter routing operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Oct 23 19:16:30 2007 " "Info: Processing ended: Tue Oct 23 19:16:30 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}