adcdac.vhd

简易示波器的VHDL程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adcdac is 
 port ( clk   : in std_logic;
        lm311 : in std_logic;
        clr   : in std_logic;
        dd    : out std_logic_vector ( 7 downto 0 );
        dispdata : out std_logic_vector ( 7 downto 0 ) );
end entity adcdac;

architecture behave_adcdac of adcdac is
   signal cqi : std_logic_vector ( 7 downto 0 );
begin
     dd <= cqi;
process ( clk, clr, lm311 )
    begin
      if clr = '1' then  cqi <= ( others => '0' );
        elsif clk'event and clk = '1' then
            if lm311 = '1' then 
               cqi <= cqi +1;
             end if;
         end if;
 end process;
 dispdata <= cqi when lm311 = '0' else "00000000";
end behave_adcdac;