adcdac.tan.rpt

简易示波器的VHDL程序

+---------------------------------------------------------------------------+
; Minimum tpd                                                               ;
+---------------+-------------------+-----------------+-------+-------------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From  ; To          ;
+---------------+-------------------+-----------------+-------+-------------+
; N/A           ; None              ; 9.912 ns        ; lm311 ; dispdata[0] ;
; N/A           ; None              ; 10.015 ns       ; lm311 ; dispdata[2] ;
; N/A           ; None              ; 10.028 ns       ; lm311 ; dispdata[3] ;
; N/A           ; None              ; 10.029 ns       ; lm311 ; dispdata[1] ;
; N/A           ; None              ; 10.353 ns       ; lm311 ; dispdata[7] ;
; N/A           ; None              ; 10.463 ns       ; lm311 ; dispdata[4] ;
; N/A           ; None              ; 10.465 ns       ; lm311 ; dispdata[5] ;
; N/A           ; None              ; 10.475 ns       ; lm311 ; dispdata[6] ;
+---------------+-------------------+-----------------+-------+-------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Oct 23 19:16:37 2007
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off adcdac -c adcdac --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 275.03 MHz between source register lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] and destination register lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.266 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]'
            Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X52_Y20_N1; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT0'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X52_Y20_N2; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT0'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X52_Y20_N3; Fanout = 2; COMB Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT0'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X52_Y20_N4; Fanout = 3; COMB Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X52_Y20_N5; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5]'
            Info: Total cell delay = 1.737 ns ( 76.65 % )
            Info: Total interconnect delay = 0.529 ns ( 23.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 3.161 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N5; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5]'
                Info: Total cell delay = 2.180 ns ( 68.97 % )
                Info: Total interconnect delay = 0.981 ns ( 31.03 % )
            Info: - Longest clock path from clock clk to source register is 3.161 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'
                Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]'
                Info: Total cell delay = 2.180 ns ( 68.97 % )
                Info: Total interconnect delay = 0.981 ns ( 31.03 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] (data pin = lm311, clock pin = clk) is 4.336 ns
    Info: + Longest pin to register delay is 7.460 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'
        Info: 2: + IC(5.124 ns) + CELL(0.867 ns) = 7.460 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7]'
        Info: Total cell delay = 2.336 ns ( 31.31 % )
        Info: Total interconnect delay = 5.124 ns ( 68.69 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock clk to destination register is 3.161 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7]'
        Info: Total cell delay = 2.180 ns ( 68.97 % )
        Info: Total interconnect delay = 0.981 ns ( 31.03 % )
Info: tco from clock clk to destination pin dd[1] through register lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] is 12.761 ns
    Info: + Longest clock path from clock clk to source register is 3.161 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]'
        Info: Total cell delay = 2.180 ns ( 68.97 % )
        Info: Total interconnect delay = 0.981 ns ( 31.03 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 9.376 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y20_N1; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]'
        Info: 2: + IC(7.252 ns) + CELL(2.124 ns) = 9.376 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'dd[1]'
        Info: Total cell delay = 2.124 ns ( 22.65 % )
        Info: Total interconnect delay = 7.252 ns ( 77.35 % )
Info: Longest tpd from source pin lm311 to destination pin dispdata[6] is 10.475 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'
    Info: 2: + IC(5.236 ns) + CELL(0.114 ns) = 6.819 ns; Loc. = LC_X52_Y21_N6; Fanout = 1; COMB Node = 'dispdata~9'
    Info: 3: + IC(1.532 ns) + CELL(2.124 ns) = 10.475 ns; Loc. = PIN_167; Fanout = 0; PIN Node = 'dispdata[6]'
    Info: Total cell delay = 3.707 ns ( 35.39 % )
    Info: Total interconnect delay = 6.768 ns ( 64.61 % )
Info: th for register lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] (data pin = lm311, clock pin = clk) is -4.284 ns
    Info: + Longest clock path from clock clk to destination register is 3.161 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7]'
        Info: Total cell delay = 2.180 ns ( 68.97 % )
        Info: Total interconnect delay = 0.981 ns ( 31.03 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.460 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'
        Info: 2: + IC(5.124 ns) + CELL(0.867 ns) = 7.460 ns; Loc. = LC_X52_Y20_N7; Fanout = 3; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7]'
        Info: Total cell delay = 2.336 ns ( 31.31 % )
        Info: Total interconnect delay = 5.124 ns ( 68.69 % )
Info: Minimum tco from clock clk to destination pin dispdata[0] through register lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] is 7.568 ns
    Info: + Shortest clock path from clock clk to source register is 3.161 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.981 ns) + CELL(0.711 ns) = 3.161 ns; Loc. = LC_X52_Y20_N0; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]'
        Info: Total cell delay = 2.180 ns ( 68.97 % )
        Info: Total interconnect delay = 0.981 ns ( 31.03 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Shortest register to pin delay is 4.183 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y20_N0; Fanout = 5; REG Node = 'lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]'
        Info: 2: + IC(0.529 ns) + CELL(0.442 ns) = 0.971 ns; Loc. = LC_X52_Y20_N8; Fanout = 1; COMB Node = 'dispdata~15'
        Info: 3: + IC(1.088 ns) + CELL(2.124 ns) = 4.183 ns; Loc. = PIN_161; Fanout = 0; PIN Node = 'dispdata[0]'
        Info: Total cell delay = 2.566 ns ( 61.34 % )
        Info: Total interconnect delay = 1.617 ns ( 38.66 % )
Info: Shortest tpd from source pin lm311 to destination pin dispdata[0] is 9.912 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 16; PIN Node = 'lm311'
    Info: 2: + IC(5.117 ns) + CELL(0.114 ns) = 6.700 ns; Loc. = LC_X52_Y20_N8; Fanout = 1; COMB Node = 'dispdata~15'
    Info: 3: + IC(1.088 ns) + CELL(2.124 ns) = 9.912 ns; Loc. = PIN_161; Fanout = 0; PIN Node = 'dispdata[0]'
    Info: Total cell delay = 3.707 ns ( 37.40 % )
    Info: Total interconnect delay = 6.205 ns ( 62.60 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Oct 23 19:16:38 2007
    Info: Elapsed time: 00:00:00