📄 adcdac.fit.rpt
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; - dispdata~9 ; 0 ; ON ;
; - dispdata~10 ; 0 ; ON ;
; - dispdata~11 ; 0 ; ON ;
; - dispdata~12 ; 0 ; ON ;
; - dispdata~13 ; 0 ; ON ;
; - dispdata~14 ; 0 ; ON ;
; - dispdata~15 ; 0 ; ON ;
; clk ; ; ;
; clr ; ; ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella7 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella6 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella5 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella3 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella2 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella1 ; 0 ; ON ;
; - lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella0 ; 0 ; ON ;
+---------------------------------------------------------------------+-------------------+---------+
+----------------------------------------------------------------------------------------------+
; Control Signals ;
+-------+----------+---------+--------------+--------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------+----------+---------+--------------+--------+----------------------+------------------+
; clk ; PIN_28 ; 8 ; Clock ; yes ; Global clock ; GCLK2 ;
; clr ; PIN_233 ; 8 ; Async. clear ; yes ; Global clock ; GCLK3 ;
; lm311 ; PIN_158 ; 16 ; Clock enable ; no ; -- ; -- ;
+-------+----------+---------+--------------+--------+----------------------+------------------+
+---------------------------------------------------------------------+
; Global & Other Fast Signals ;
+------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+------+----------+---------+----------------------+------------------+
; clk ; PIN_28 ; 8 ; Global clock ; GCLK2 ;
; clr ; PIN_233 ; 8 ; Global clock ; GCLK3 ;
+------+----------+---------+----------------------+------------------+
+-----------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-------------------------------------------------------------------+---------+
; lm311 ; 16 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|counter_cella4~COUT ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[4] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[6] ; 3 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[7] ; 3 ;
; dispdata~15 ; 1 ;
; dispdata~14 ; 1 ;
; dispdata~13 ; 1 ;
; dispdata~12 ; 1 ;
; dispdata~11 ; 1 ;
; dispdata~10 ; 1 ;
; dispdata~9 ; 1 ;
; dispdata~8 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]~COUT1 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[0]~COUT0 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT1 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[1]~COUT0 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT1 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[2]~COUT0 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT1 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[3]~COUT0 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5]~COUT1 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[5]~COUT0 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[6]~COUT1 ; 1 ;
; lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated|safe_q[6]~COUT0 ; 1 ;
+-------------------------------------------------------------------+---------+
+----------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 46 / 30,600 ( < 1 % ) ;
; Direct links ; 4 / 43,552 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
; LAB clocks ; 2 / 312 ( < 1 % ) ;
; LUT chains ; 0 / 10,854 ( 0 % ) ;
; Local interconnects ; 26 / 43,552 ( < 1 % ) ;
; M4K buffers ; 0 / 1,872 ( 0 % ) ;
; R4s ; 29 / 28,560 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 8.00) ; Number of LABs (Total = 2) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 2) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 1 ;
; 1 Clock ; 1 ;
; 1 Clock enable ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 8.00) ; Number of LABs (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ⌨️ 快捷键说明
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