adcdac.map.rpt

简易示波器的VHDL程序

+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 8     ;
; Number of synthesis-generated cells                    ; 8     ;
; Number of WYSIWYG LUTs                                 ; 8     ;
; Number of synthesis-generated LUTs                     ; 8     ;
; Number of WYSIWYG registers                            ; 8     ;
; Number of synthesis-generated registers                ; 0     ;
; Number of cells with combinational logic only          ; 8     ;
; Number of cells with registers only                    ; 0     ;
; Number of cells with combinational logic and registers ; 8     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
adcdac
 |-- lpm_counter:cqi_rtl_0
      |-- cntr_uu7:auto_generated


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                              ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------+
; Compilation Hierarchy Node      ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                   ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------+
; |adcdac                         ; 16 (8)      ; 8            ; 0           ; 19   ; 0            ; 8 (8)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |adcdac                                               ;
;    |lpm_counter:cqi_rtl_0|      ; 8 (0)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |adcdac|lpm_counter:cqi_rtl_0                         ;
;       |cntr_uu7:auto_generated| ; 8 (8)       ; 8            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |adcdac|lpm_counter:cqi_rtl_0|cntr_uu7:auto_generated ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/highflu documents/quartwork/adcdac/adcdac.map.eqn.


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------+-----------------+
; File Name                                                    ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; adcdac.vhd                                                   ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; E:/highflu documents/quartwork/adcdac/db/cntr_uu7.tdf        ; yes             ;
+--------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 16      ;
; Total combinational functions     ; 16      ;
; Total 4-input functions           ; 0       ;
; Total 3-input functions           ; 0       ;
; Total 2-input functions           ; 8       ;
; Total 1-input functions           ; 8       ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 8       ;
; Total logic cells in carry chains ; 8       ;
; I/O pins                          ; 19      ;
; Maximum fan-out node              ; lm311   ;
; Maximum fan-out                   ; 16      ;
; Total fan-out                     ; 71      ;
; Average fan-out                   ; 2.03    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Oct 23 19:16:16 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off adcdac -c adcdac
Info: Found 2 design units, including 1 entities, in source file adcdac.vhd
    Info: Found design unit 1: adcdac-behave_adcdac
    Info: Found entity 1: adcdac
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: cqi[0]~0
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_uu7.tdf
    Info: Found entity 1: cntr_uu7
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
    Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Oct 23 19:16:20 2007
    Info: Elapsed time: 00:00:04