📄 motor.map.rpt
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Analysis & Synthesis report for motor
Fri Oct 26 21:50:36 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Oct 26 21:50:36 2007 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; motor ;
; Top-level Entity Name ; motor ;
; Family ; Cyclone ;
; Total logic elements ; 0 ;
; Total pins ; 3 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EP1C12Q240C8 ; ;
; Top-level entity name ; motor ; motor ;
; Family name ; Cyclone ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; -1 ; -1 ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------+
; decd.vhd ; yes ; User VHDL File ; E:/WORKS/QurIIwork/direct-motor/decd.vhd ;
; cnt5.vhd ; yes ; User VHDL File ; E:/WORKS/QurIIwork/direct-motor/cnt5.vhd ;
; motor.bdf ; yes ; User Block Diagram/Schematic File ; E:/WORKS/QurIIwork/direct-motor/motor.bdf ;
+----------------------------------+-----------------+------------------------------------+-------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource ; Usage ;
+---------------------------------+-----------+
; Total logic elements ; 0 ;
; Total combinational functions ; 0 ;
; -- Total 4-input functions ; 0 ;
; -- Total 3-input functions ; 0 ;
; -- Total 2-input functions ; 0 ;
; -- Total 1-input functions ; 0 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 0 ;
; I/O pins ; 3 ;
+---------------------------------+-----------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |motor ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |motor ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 0 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/WORKS/QurIIwork/direct-motor/motor.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Fri Oct 26 21:50:34 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off motor -c motor
Info: Found 2 design units, including 1 entities, in source file decd.vhd
Info: Found design unit 1: decd-behave_decd
Info: Found entity 1: decd
Info: Found 2 design units, including 1 entities, in source file cnt5.vhd
Info: Found design unit 1: cnt5-behave_cnt5
Info: Found entity 1: cnt5
Info: Found 1 design units, including 1 entities, in source file motor.bdf
Info: Found entity 1: motor
Info: Elaborating entity "motor" for the top level hierarchy
Info: Elaborating entity "decd" for hierarchy "decd:inst1"
Info: VHDL Case Statement information at decd.vhd(22): OTHERS choice is never selected
Warning: Output port "dspy[1]" at decd.vhd(7) has no driver
Warning: Output port "dspy[0]" at decd.vhd(7) has no driver
Info: Elaborating entity "cnt5" for hierarchy "cnt5:inst"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "dled[1]" stuck at GND
Warning: Pin "dled[0]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "pin_name"
Info: Implemented 3 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 2 output pins
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Fri Oct 26 21:50:36 2007
Info: Elapsed time: 00:00:02
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