cnt5.vhd

来自「直流电机的程序」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
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entity cnt5 is
port ( clk : in std_logic;
       aa : out std_logic_vector ( 4 downto 1 ) );
end entity cnt5;
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architecture behave_cnt5 of cnt5 is
    signal cqi : std_logic_vector ( 4 downto 0 );
begin
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process ( clk )
   begin
      if clk'event and clk = '1' then
         cqi <= cqi +1;
       end if;
end process;
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aa <= cqi ( 4 downto 1 );
end behave_cnt5;