decd.vhd

来自「直流电机的程序」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------
entity decd is 
port ( clk  : in std_logic;
       dspy : out std_logic_vector ( 1 downto 0 );
         d  : out std_logic_vector ( 3 downto 0 ) );
end entity decd;
----------------------------------------------------
architecture behave_decd of decd is
signal cq : std_logic_vector ( 1 downto 0 );
begin
-------------------------------------------------
   process ( cq )
     begin
       case cq is
          when "00" => d <= "0100";
          when "01" => d <= "0111";
          when "10" => d <= "1011";   
          when "11" => d <= "1111";
          when others => null;
        end case;
     end process;
-------------------------------------------------
  process ( clk )
    begin
     if clk'event and clk = '1' then
        cq <= cq +1 ;
     end if;
   end process;
----------------------------------------------------
end behave_decd;