reg32b.vhd

用VHDL语言设计的频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reg32b is
   port ( lk : in std_logic;
         din : in std_logic_vector ( 31 downto 0 );
        dout : out std_logic_vector ( 31 downto 0 ) ) ;
end entity reg32b;

architecture behave_reg32b of reg32b is 
  begin 
  process ( lk , din )
  begin
  if lk'event and lk = '1' then 
     dout <= din;
  end if;
  end process;
end behave_reg32b;