freqtest.fit.qmsg

用VHDL语言设计的频率计

{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.020 ns register register " "Info: Estimated most critical path is register to register delay of 5.020 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter32b:u3\|cqi\[5\] 1 REG LAB_X13_Y11 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y11; Fanout = 8; REG Node = 'counter32b:u3\|cqi\[5\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { counter32b:u3|cqi[5] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(0.442 ns) 1.318 ns counter32b:u3\|LessThan~117 2 COMB LAB_X12_Y10 8 " "Info: 2: + IC(0.876 ns) + CELL(0.442 ns) = 1.318 ns; Loc. = LAB_X12_Y10; Fanout = 8; COMB Node = 'counter32b:u3\|LessThan~117'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.318 ns" { counter32b:u3|cqi[5] counter32b:u3|LessThan~117 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.285 ns) + CELL(0.292 ns) 1.895 ns counter32b:u3\|cqi~3974 3 COMB LAB_X12_Y10 6 " "Info: 3: + IC(0.285 ns) + CELL(0.292 ns) = 1.895 ns; Loc. = LAB_X12_Y10; Fanout = 6; COMB Node = 'counter32b:u3\|cqi~3974'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "0.577 ns" { counter32b:u3|LessThan~117 counter32b:u3|cqi~3974 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(-0.013 ns) + CELL(0.590 ns) 2.472 ns counter32b:u3\|cqi~3979 4 COMB LAB_X12_Y10 3 " "Info: 4: + IC(-0.013 ns) + CELL(0.590 ns) = 2.472 ns; Loc. = LAB_X12_Y10; Fanout = 3; COMB Node = 'counter32b:u3\|cqi~3979'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "0.577 ns" { counter32b:u3|cqi~3974 counter32b:u3|cqi~3979 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.128 ns) + CELL(0.114 ns) 3.714 ns counter32b:u3\|cqi~3981 5 COMB LAB_X12_Y9 1 " "Info: 5: + IC(1.128 ns) + CELL(0.114 ns) = 3.714 ns; Loc. = LAB_X12_Y9; Fanout = 1; COMB Node = 'counter32b:u3\|cqi~3981'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.242 ns" { counter32b:u3|cqi~3979 counter32b:u3|cqi~3981 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.191 ns) + CELL(0.115 ns) 5.020 ns counter32b:u3\|cqi\[26\] 6 REG LAB_X13_Y8 7 " "Info: 6: + IC(1.191 ns) + CELL(0.115 ns) = 5.020 ns; Loc. = LAB_X13_Y8; Fanout = 7; REG Node = 'counter32b:u3\|cqi\[26\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.306 ns" { counter32b:u3|cqi~3981 counter32b:u3|cqi[26] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.553 ns 30.94 % " "Info: Total cell delay = 1.553 ns ( 30.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.467 ns 69.06 % " "Info: Total interconnect delay = 3.467 ns ( 69.06 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "5.020 ns" { counter32b:u3|cqi[5] counter32b:u3|LessThan~117 counter32b:u3|cqi~3974 counter32b:u3|cqi~3979 counter32b:u3|cqi~3981 counter32b:u3|cqi[26] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "2 " "Info: Fitter routing operations ending: elapsed time = 2 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 20 13:49:50 2007 " "Info: Processing ended: Sat Oct 20 13:49:50 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}