freqtest.fit.qmsg

用VHDL语言设计的频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 20 13:49:40 2007 " "Info: Processing started: Sat Oct 20 13:49:40 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off freqtest -c freqtest " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off freqtest -c freqtest" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "freqtest EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design freqtest" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fsin Global clock in PIN 152 " "Info: Automatically promoted signal fsin to use Global clock in PIN 152" {  } { { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 7 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "ftctrl:u1\|div2clk Global clock " "Info: Automatically promoted some destinations of signal ftctrl:u1\|div2clk to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[31\] " "Info: Destination counter32b:u3\|cqi\[31\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ftctrl:u1\|div2clk " "Info: Destination ftctrl:u1\|div2clk may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[30\] " "Info: Destination counter32b:u3\|cqi\[30\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[29\] " "Info: Destination counter32b:u3\|cqi\[29\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[28\] " "Info: Destination counter32b:u3\|cqi\[28\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[27\] " "Info: Destination counter32b:u3\|cqi\[27\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[26\] " "Info: Destination counter32b:u3\|cqi\[26\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[25\] " "Info: Destination counter32b:u3\|cqi\[25\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[24\] " "Info: Destination counter32b:u3\|cqi\[24\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "counter32b:u3\|cqi\[23\] " "Info: Destination counter32b:u3\|cqi\[23\] may be non-global or may not use global clock" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "ftctrl:u1\|rst_cnt Global clock " "Info: Automatically promoted signal ftctrl:u1\|rst_cnt to use Global clock" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}