freqtest.tan.qmsg

用VHDL语言设计的频率计

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk1hz dout\[9\] reg32b:u2\|dout\[9\] 12.207 ns register " "Info: Minimum tco from clock clk1hz to destination pin dout\[9\] through register reg32b:u2\|dout\[9\] is 12.207 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1hz source 7.312 ns + Shortest register " "Info: + Shortest clock path from clock clk1hz to source register is 7.312 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1hz 1 CLK PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 2; CLK Node = 'clk1hz'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { clk1hz } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.935 ns) 3.322 ns ftctrl:u1\|div2clk 2 REG LC_X8_Y13_N4 66 " "Info: 2: + IC(0.918 ns) + CELL(0.935 ns) = 3.322 ns; Loc. = LC_X8_Y13_N4; Fanout = 66; REG Node = 'ftctrl:u1\|div2clk'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.853 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.279 ns) + CELL(0.711 ns) 7.312 ns reg32b:u2\|dout\[9\] 3 REG LC_X12_Y8_N9 1 " "Info: 3: + IC(3.279 ns) + CELL(0.711 ns) = 7.312 ns; Loc. = LC_X12_Y8_N9; Fanout = 1; REG Node = 'reg32b:u2\|dout\[9\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.990 ns" { ftctrl:u1|div2clk reg32b:u2|dout[9] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.60 % " "Info: Total cell delay = 3.115 ns ( 42.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.197 ns 57.40 % " "Info: Total interconnect delay = 4.197 ns ( 57.40 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "7.312 ns" { clk1hz ftctrl:u1|div2clk reg32b:u2|dout[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.671 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg32b:u2\|dout\[9\] 1 REG LC_X12_Y8_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N9; Fanout = 1; REG Node = 'reg32b:u2\|dout\[9\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { reg32b:u2|dout[9] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.547 ns) + CELL(2.124 ns) 4.671 ns dout\[9\] 2 PIN PIN_41 0 " "Info: 2: + IC(2.547 ns) + CELL(2.124 ns) = 4.671 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'dout\[9\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "4.671 ns" { reg32b:u2|dout[9] dout[9] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 45.47 % " "Info: Total cell delay = 2.124 ns ( 45.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.547 ns 54.53 % " "Info: Total interconnect delay = 2.547 ns ( 54.53 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "4.671 ns" { reg32b:u2|dout[9] dout[9] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "7.312 ns" { clk1hz ftctrl:u1|div2clk reg32b:u2|dout[9] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "4.671 ns" { reg32b:u2|dout[9] dout[9] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 20 13:49:57 2007 " "Info: Processing ended: Sat Oct 20 13:49:57 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}