freqtest.tan.qmsg

用VHDL语言设计的频率计

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ftctrl:u1\|div2clk " "Info: Detected ripple clock ftctrl:u1\|div2clk as buffer" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "ftctrl:u1\|div2clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk1hz register register ftctrl:u1\|div2clk ftctrl:u1\|div2clk 275.03 MHz Internal " "Info: Clock clk1hz Internal fmax is restricted to 275.03 MHz between source register ftctrl:u1\|div2clk and destination register ftctrl:u1\|div2clk" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.028 ns + Longest register register " "Info: + Longest register to register delay is 1.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ftctrl:u1\|div2clk 1 REG LC_X8_Y13_N4 66 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y13_N4; Fanout = 66; REG Node = 'ftctrl:u1\|div2clk'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.478 ns) 1.028 ns ftctrl:u1\|div2clk 2 REG LC_X8_Y13_N4 66 " "Info: 2: + IC(0.550 ns) + CELL(0.478 ns) = 1.028 ns; Loc. = LC_X8_Y13_N4; Fanout = 66; REG Node = 'ftctrl:u1\|div2clk'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.028 ns" { ftctrl:u1|div2clk ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 46.50 % " "Info: Total cell delay = 0.478 ns ( 46.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 53.50 % " "Info: Total interconnect delay = 0.550 ns ( 53.50 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.028 ns" { ftctrl:u1|div2clk ftctrl:u1|div2clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1hz destination 3.098 ns + Shortest register " "Info: + Shortest clock path from clock clk1hz to destination register is 3.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1hz 1 CLK PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 2; CLK Node = 'clk1hz'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { clk1hz } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.711 ns) 3.098 ns ftctrl:u1\|div2clk 2 REG LC_X8_Y13_N4 66 " "Info: 2: + IC(0.918 ns) + CELL(0.711 ns) = 3.098 ns; Loc. = LC_X8_Y13_N4; Fanout = 66; REG Node = 'ftctrl:u1\|div2clk'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.629 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.37 % " "Info: Total cell delay = 2.180 ns ( 70.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.918 ns 29.63 % " "Info: Total interconnect delay = 0.918 ns ( 29.63 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.098 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1hz source 3.098 ns - Longest register " "Info: - Longest clock path from clock clk1hz to source register is 3.098 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1hz 1 CLK PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 2; CLK Node = 'clk1hz'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { clk1hz } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.711 ns) 3.098 ns ftctrl:u1\|div2clk 2 REG LC_X8_Y13_N4 66 " "Info: 2: + IC(0.918 ns) + CELL(0.711 ns) = 3.098 ns; Loc. = LC_X8_Y13_N4; Fanout = 66; REG Node = 'ftctrl:u1\|div2clk'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.629 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.37 % " "Info: Total cell delay = 2.180 ns ( 70.37 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.918 ns 29.63 % " "Info: Total interconnect delay = 0.918 ns ( 29.63 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.098 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.098 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.098 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.028 ns" { ftctrl:u1|div2clk ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.098 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.098 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "fsin register counter32b:u3\|cqi\[9\] register counter32b:u3\|cqi\[26\] 157.75 MHz 6.339 ns Internal " "Info: Clock fsin has Internal fmax of 157.75 MHz between source register counter32b:u3\|cqi\[9\] and destination register counter32b:u3\|cqi\[26\] (period= 6.339 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.078 ns + Longest register register " "Info: + Longest register to register delay is 6.078 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter32b:u3\|cqi\[9\] 1 REG LC_X13_Y10_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y10_N3; Fanout = 8; REG Node = 'counter32b:u3\|cqi\[9\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { counter32b:u3|cqi[9] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.169 ns) + CELL(0.590 ns) 1.759 ns counter32b:u3\|LessThan~101 2 COMB LC_X12_Y10_N0 8 " "Info: 2: + IC(1.169 ns) + CELL(0.590 ns) = 1.759 ns; Loc. = LC_X12_Y10_N0; Fanout = 8; COMB Node = 'counter32b:u3\|LessThan~101'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.759 ns" { counter32b:u3|cqi[9] counter32b:u3|LessThan~101 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.424 ns) + CELL(0.442 ns) 2.625 ns counter32b:u3\|cqi~3974 3 COMB LC_X12_Y10_N2 6 " "Info: 3: + IC(0.424 ns) + CELL(0.442 ns) = 2.625 ns; Loc. = LC_X12_Y10_N2; Fanout = 6; COMB Node = 'counter32b:u3\|cqi~3974'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "0.866 ns" { counter32b:u3|LessThan~101 counter32b:u3|cqi~3974 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.292 ns) 3.382 ns counter32b:u3\|cqi~3979 4 COMB LC_X12_Y10_N6 3 " "Info: 4: + IC(0.465 ns) + CELL(0.292 ns) = 3.382 ns; Loc. = LC_X12_Y10_N6; Fanout = 3; COMB Node = 'counter32b:u3\|cqi~3979'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "0.757 ns" { counter32b:u3|cqi~3974 counter32b:u3|cqi~3979 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.242 ns) + CELL(0.114 ns) 4.738 ns counter32b:u3\|cqi~3981 5 COMB LC_X12_Y9_N7 1 " "Info: 5: + IC(1.242 ns) + CELL(0.114 ns) = 4.738 ns; Loc. = LC_X12_Y9_N7; Fanout = 1; COMB Node = 'counter32b:u3\|cqi~3981'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.356 ns" { counter32b:u3|cqi~3979 counter32b:u3|cqi~3981 } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.225 ns) + CELL(0.115 ns) 6.078 ns counter32b:u3\|cqi\[26\] 6 REG LC_X13_Y8_N0 7 " "Info: 6: + IC(1.225 ns) + CELL(0.115 ns) = 6.078 ns; Loc. = LC_X13_Y8_N0; Fanout = 7; REG Node = 'counter32b:u3\|cqi\[26\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.340 ns" { counter32b:u3|cqi~3981 counter32b:u3|cqi[26] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.553 ns 25.55 % " "Info: Total cell delay = 1.553 ns ( 25.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.525 ns 74.45 % " "Info: Total interconnect delay = 4.525 ns ( 74.45 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "6.078 ns" { counter32b:u3|cqi[9] counter32b:u3|LessThan~101 counter32b:u3|cqi~3974 counter32b:u3|cqi~3979 counter32b:u3|cqi~3981 counter32b:u3|cqi[26] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fsin destination 3.147 ns + Shortest register " "Info: + Shortest clock path from clock fsin to destination register is 3.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fsin 1 CLK PIN_152 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 32; CLK Node = 'fsin'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { fsin } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.711 ns) 3.147 ns counter32b:u3\|cqi\[26\] 2 REG LC_X13_Y8_N0 7 " "Info: 2: + IC(0.967 ns) + CELL(0.711 ns) = 3.147 ns; Loc. = LC_X13_Y8_N0; Fanout = 7; REG Node = 'counter32b:u3\|cqi\[26\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.678 ns" { fsin counter32b:u3|cqi[26] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 69.27 % " "Info: Total cell delay = 2.180 ns ( 69.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.967 ns 30.73 % " "Info: Total interconnect delay = 0.967 ns ( 30.73 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.147 ns" { fsin counter32b:u3|cqi[26] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "fsin source 3.147 ns - Longest register " "Info: - Longest clock path from clock fsin to source register is 3.147 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fsin 1 CLK PIN_152 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 32; CLK Node = 'fsin'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { fsin } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.711 ns) 3.147 ns counter32b:u3\|cqi\[9\] 2 REG LC_X13_Y10_N3 8 " "Info: 2: + IC(0.967 ns) + CELL(0.711 ns) = 3.147 ns; Loc. = LC_X13_Y10_N3; Fanout = 8; REG Node = 'counter32b:u3\|cqi\[9\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.678 ns" { fsin counter32b:u3|cqi[9] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 69.27 % " "Info: Total cell delay = 2.180 ns ( 69.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.967 ns 30.73 % " "Info: Total interconnect delay = 0.967 ns ( 30.73 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.147 ns" { fsin counter32b:u3|cqi[9] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.147 ns" { fsin counter32b:u3|cqi[26] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.147 ns" { fsin counter32b:u3|cqi[9] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 18 -1 0 } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "6.078 ns" { counter32b:u3|cqi[9] counter32b:u3|LessThan~101 counter32b:u3|cqi~3974 counter32b:u3|cqi~3979 counter32b:u3|cqi~3981 counter32b:u3|cqi[26] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.147 ns" { fsin counter32b:u3|cqi[26] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.147 ns" { fsin counter32b:u3|cqi[9] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1hz dout\[29\] reg32b:u2\|dout\[29\] 15.994 ns register " "Info: tco from clock clk1hz to destination pin dout\[29\] through register reg32b:u2\|dout\[29\] is 15.994 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1hz source 7.312 ns + Longest register " "Info: + Longest clock path from clock clk1hz to source register is 7.312 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1hz 1 CLK PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 2; CLK Node = 'clk1hz'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { clk1hz } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.935 ns) 3.322 ns ftctrl:u1\|div2clk 2 REG LC_X8_Y13_N4 66 " "Info: 2: + IC(0.918 ns) + CELL(0.935 ns) = 3.322 ns; Loc. = LC_X8_Y13_N4; Fanout = 66; REG Node = 'ftctrl:u1\|div2clk'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "1.853 ns" { clk1hz ftctrl:u1|div2clk } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.279 ns) + CELL(0.711 ns) 7.312 ns reg32b:u2\|dout\[29\] 3 REG LC_X14_Y8_N2 1 " "Info: 3: + IC(3.279 ns) + CELL(0.711 ns) = 7.312 ns; Loc. = LC_X14_Y8_N2; Fanout = 1; REG Node = 'reg32b:u2\|dout\[29\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "3.990 ns" { ftctrl:u1|div2clk reg32b:u2|dout[29] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 42.60 % " "Info: Total cell delay = 3.115 ns ( 42.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.197 ns 57.40 % " "Info: Total interconnect delay = 4.197 ns ( 57.40 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "7.312 ns" { clk1hz ftctrl:u1|div2clk reg32b:u2|dout[29] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.458 ns + Longest register pin " "Info: + Longest register to pin delay is 8.458 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg32b:u2\|dout\[29\] 1 REG LC_X14_Y8_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y8_N2; Fanout = 1; REG Node = 'reg32b:u2\|dout\[29\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "" { reg32b:u2|dout[29] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.334 ns) + CELL(2.124 ns) 8.458 ns dout\[29\] 2 PIN PIN_166 0 " "Info: 2: + IC(6.334 ns) + CELL(2.124 ns) = 8.458 ns; Loc. = PIN_166; Fanout = 0; PIN Node = 'dout\[29\]'" {  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "8.458 ns" { reg32b:u2|dout[29] dout[29] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 25.11 % " "Info: Total cell delay = 2.124 ns ( 25.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.334 ns 74.89 % " "Info: Total interconnect delay = 6.334 ns ( 74.89 % )" {  } {  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "8.458 ns" { reg32b:u2|dout[29] dout[29] } "NODE_NAME" } } }  } 0}  } { { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "7.312 ns" { clk1hz ftctrl:u1|div2clk reg32b:u2|dout[29] } "NODE_NAME" } } } { "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" "" "" { Report "E:/highflu documents/quartwork/freqtest/db/freqtest_cmp.qrpt" Compiler "freqtest" "UNKNOWN" "V1" "E:/highflu documents/quartwork/freqtest/db/freqtest.quartus_db" { Floorplan "" "" "8.458 ns" { reg32b:u2|dout[29] dout[29] } "NODE_NAME" } } }  } 0}