freqtest.tan.qmsg

用VHDL语言设计的频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 20 13:49:56 2007 " "Info: Processing started: Sat Oct 20 13:49:56 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off freqtest -c freqtest --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off freqtest -c freqtest --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1hz " "Info: Assuming node clk1hz is an undefined clock" {  } { { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk1hz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "fsin " "Info: Assuming node fsin is an undefined clock" {  } { { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 7 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "fsin" } } } }  } 0}  } {  } 0}