freqtest.map.qmsg

用VHDL语言设计的频率计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 20 13:49:35 2007 " "Info: Processing started: Sat Oct 20 13:49:35 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off freqtest -c freqtest " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off freqtest -c freqtest" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ftctrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ftctrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ftctrl-behave_ftctrl " "Info: Found design unit 1: ftctrl-behave_ftctrl" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "ftctrl-behave_ftctrl" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ftctrl " "Info: Found entity 1: ftctrl" {  } { { "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" "ftctrl" "" { Text "E:/highflu documents/quartwork/freqtest/ftctrl.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg32b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg32b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg32b-behave_reg32b " "Info: Found design unit 1: reg32b-behave_reg32b" {  } { { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "reg32b-behave_reg32b" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 reg32b " "Info: Found entity 1: reg32b" {  } { { "E:/highflu documents/quartwork/freqtest/reg32b.vhd" "reg32b" "" { Text "E:/highflu documents/quartwork/freqtest/reg32b.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter32b.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter32b.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter32b-behave_counter32b " "Info: Found design unit 1: counter32b-behave_counter32b" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "counter32b-behave_counter32b" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 counter32b " "Info: Found entity 1: counter32b" {  } { { "E:/highflu documents/quartwork/freqtest/counter32b.vhd" "counter32b" "" { Text "E:/highflu documents/quartwork/freqtest/counter32b.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "freqtest.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file freqtest.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 freqtest-behave_freqtest " "Info: Found design unit 1: freqtest-behave_freqtest" {  } { { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "freqtest-behave_freqtest" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 freqtest " "Info: Found entity 1: freqtest" {  } { { "E:/highflu documents/quartwork/freqtest/freqtest.vhd" "freqtest" "" { Text "E:/highflu documents/quartwork/freqtest/freqtest.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gate_clk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gate_clk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gate_clk-behave_gateclk " "Info: Found design unit 1: gate_clk-behave_gateclk" {  } { { "E:/highflu documents/quartwork/freqtest/gate_clk.vhd" "gate_clk-behave_gateclk" "" { Text "E:/highflu documents/quartwork/freqtest/gate_clk.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 gate_clk " "Info: Found entity 1: gate_clk" {  } { { "E:/highflu documents/quartwork/freqtest/gate_clk.vhd" "gate_clk" "" { Text "E:/highflu documents/quartwork/freqtest/gate_clk.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "conver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file conver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 conver-behave " "Info: Found design unit 1: conver-behave" {  } { { "E:/highflu documents/quartwork/freqtest/conver.vhd" "conver-behave" "" { Text "E:/highflu documents/quartwork/freqtest/conver.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 conver " "Info: Found entity 1: conver" {  } { { "E:/highflu documents/quartwork/freqtest/conver.vhd" "conver" "" { Text "E:/highflu documents/quartwork/freqtest/conver.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "154 " "Info: Implemented 154 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "32 " "Info: Implemented 32 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "120 " "Info: Implemented 120 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 20 13:49:39 2007 " "Info: Processing ended: Sat Oct 20 13:49:39 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}