gate_clk.vhd

用VHDL语言设计的频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity gate_clk is
    port ( clk : in std_logic;
             f : in std_logic;
        outclk : out std_logic );
end entity gate_clk;

architecture behave_gateclk of gate_clk is
      signal clkkk : std_logic;
 begin
   process ( clk ,f )
    begin
    if clk'event and clk = '1' then
      if f'event and f = '1' then
      clkkk <= '1';
      end if;
    
    elsif clk'event and clk = '1' then
      if f'event and f = '1' then
      clkkk <= '0';
      end if;
   end if;
  end process;
  outclk <= clkkk;
end behave_gateclk;