conver.vhd

来自「用VHDL语言设计的频率计」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity conver is
   port ( ddin : in std_logic_vector( 31 downto 0 );
          dateout : out std_logic_vector ( 31 downto 0 ) );
end entity conver;

architecture behave of conver is
      signal date : std_logic_vector ( 31 downto 0 );
      
begin 
  p1:process ( ddin )
     begin
       date <= ddin;
     end process p1;
  
 p2:process ( date )
    variable dd : std_logic_vector ( 31 downto 0 );
    begin

   for i in 0 to 11 loop
     if date( i ) = '1' then dd := dd + 2**i ;
     elsif date ( i ) = '0' then dd := dd ;
     end if;
   end loop;
   dateout <= dd;
  end process p2 ;
   
end behave;