freqtest.vhd

用VHDL语言设计的频率计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity freqtest is
   port ( clk1hz : in std_logic;
            fsin : in std_logic;
            dout : out std_logic_vector ( 31 downto 0 ) );
end entity freqtest;

architecture behave_freqtest of freqtest is

component ftctrl 
     port ( clkk    : in std_logic;
            cnt_en  : out std_logic;
            rst_cnt : out std_logic;
            load    : out std_logic );
end component ;

component counter32b is
        port ( fin : in std_logic;
               clr : in std_logic;
             enabl : in std_logic;
             dout  : out std_logic_vector ( 31 downto 0 ) );
end component;

component reg32b is
        port ( lk : in std_logic;
              din : in std_logic_vector ( 31 downto 0 );
             dout : out std_logic_vector ( 31 downto 0 ) ) ;
end component;
signal gateclk  : std_logic;
    signal tsten1   : std_logic;
    signal clr_cnt1 : std_logic;
    signal load1    : std_logic;
    signal dtol     : std_logic_vector ( 31 downto 0 );
    --signal dttoll   : std_logic_vector ( 31 downto 0 );
    signal carry_out1 : std_logic_vector ( 6 downto 0 );
  begin
     
     u1: ftctrl port map ( clkk => clk1hz, cnt_en=> tsten1,
                           rst_cnt => clr_cnt1, load => load1 );
     u2: reg32b port map ( lk => load1, din => dtol, dout=>dout );
     u3: counter32b port map ( fin => fsin, clr => clr_cnt1,
                               enabl => tsten1, dout => dtol );
  end behave_freqtest;