freqtest.tan.summary

用VHDL语言设计的频率计

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.994 ns
From           : reg32b:u2|dout[29]
To             : dout[29]
From Clock     : clk1hz
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.207 ns
From           : reg32b:u2|dout[9]
To             : dout[9]
From Clock     : clk1hz
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'fsin'
Slack          : N/A
Required Time  : None
Actual Time    : 157.75 MHz ( period = 6.339 ns )
From           : counter32b:u3|cqi[9]
To             : counter32b:u3|cqi[26]
From Clock     : fsin
To Clock       : fsin
Failed Paths   : 0

Type           : Clock Setup: 'clk1hz'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : ftctrl:u1|div2clk
To             : ftctrl:u1|div2clk
From Clock     : clk1hz
To Clock       : clk1hz
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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