freqtest.map.rpt

用VHDL语言设计的频率计

+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 32    ;
; Number of synthesis-generated cells                    ; 88    ;
; Number of WYSIWYG LUTs                                 ; 32    ;
; Number of synthesis-generated LUTs                     ; 55    ;
; Number of WYSIWYG registers                            ; 32    ;
; Number of synthesis-generated registers                ; 33    ;
; Number of cells with combinational logic only          ; 55    ;
; Number of cells with registers only                    ; 33    ;
; Number of cells with combinational logic and registers ; 32    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 32    ;
; Number of registers using Asynchronous Clear ; 32    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
freqtest
 |-- ftctrl:u1
 |-- reg32b:u2
 |-- counter32b:u3


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+
; |freqtest                  ; 120 (1)     ; 65           ; 0           ; 34   ; 0            ; 55 (1)       ; 33 (0)            ; 32 (0)           ; 32 (0)          ; |freqtest               ;
;    |counter32b:u3|         ; 85 (85)     ; 32           ; 0           ; 0    ; 0            ; 53 (53)      ; 0 (0)             ; 32 (32)          ; 32 (32)         ; |freqtest|counter32b:u3 ;
;    |ftctrl:u1|             ; 2 (2)       ; 1            ; 0           ; 0    ; 0            ; 1 (1)        ; 1 (1)             ; 0 (0)            ; 0 (0)           ; |freqtest|ftctrl:u1     ;
;    |reg32b:u2|             ; 32 (32)     ; 32           ; 0           ; 0    ; 0            ; 0 (0)        ; 32 (32)           ; 0 (0)            ; 0 (0)           ; |freqtest|reg32b:u2     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/highflu documents/quartwork/freqtest/freqtest.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------+-----------------------+
; File Name      ; Used in Netlist       ;
+----------------+-----------------------+
; ftctrl.vhd     ; yes                   ;
; reg32b.vhd     ; yes                   ;
; counter32b.vhd ; yes                   ;
; freqtest.vhd   ; yes                   ;
+----------------+-----------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------+-------------------+
; Resource                          ; Usage             ;
+-----------------------------------+-------------------+
; Logic cells                       ; 120               ;
; Total combinational functions     ; 87                ;
; Total 4-input functions           ; 33                ;
; Total 3-input functions           ; 13                ;
; Total 2-input functions           ; 8                 ;
; Total 1-input functions           ; 32                ;
; Total 0-input functions           ; 1                 ;
; Combinational cells for routing   ; 0                 ;
; Total registers                   ; 65                ;
; Total logic cells in carry chains ; 32                ;
; I/O pins                          ; 34                ;
; Maximum fan-out node              ; ftctrl:u1|div2clk ;
; Maximum fan-out                   ; 66                ;
; Total fan-out                     ; 508               ;
; Average fan-out                   ; 3.30              ;
+-----------------------------------+-------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat Oct 20 13:49:35 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off freqtest -c freqtest
Info: Found 2 design units, including 1 entities, in source file ftctrl.vhd
    Info: Found design unit 1: ftctrl-behave_ftctrl
    Info: Found entity 1: ftctrl
Info: Found 2 design units, including 1 entities, in source file reg32b.vhd
    Info: Found design unit 1: reg32b-behave_reg32b
    Info: Found entity 1: reg32b
Info: Found 2 design units, including 1 entities, in source file counter32b.vhd
    Info: Found design unit 1: counter32b-behave_counter32b
    Info: Found entity 1: counter32b
Info: Found 2 design units, including 1 entities, in source file freqtest.vhd
    Info: Found design unit 1: freqtest-behave_freqtest
    Info: Found entity 1: freqtest
Info: Found 2 design units, including 1 entities, in source file gate_clk.vhd
    Info: Found design unit 1: gate_clk-behave_gateclk
    Info: Found entity 1: gate_clk
Info: Found 2 design units, including 1 entities, in source file conver.vhd
    Info: Found design unit 1: conver-behave
    Info: Found entity 1: conver
Info: Implemented 154 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 32 output pins
    Info: Implemented 120 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Oct 20 13:49:39 2007
    Info: Elapsed time: 00:00:03