savagefb.c

h内核

		}
	}

	vgaHWRestore (par);

	/* extended mode timing registers */
	vga_out8 (0x3d4, 0x53);
	vga_out8 (0x3d5, par->CR53);
	vga_out8 (0x3d4, 0x5d);
	vga_out8 (0x3d5, par->CR5D);
	vga_out8 (0x3d4, 0x5e);
	vga_out8 (0x3d5, par->CR5E);
	vga_out8 (0x3d4, 0x3b);
	vga_out8 (0x3d5, par->CR3B);
	vga_out8 (0x3d4, 0x3c);
	vga_out8 (0x3d5, par->CR3C);
	vga_out8 (0x3d4, 0x43);
	vga_out8 (0x3d5, par->CR43);
	vga_out8 (0x3d4, 0x65);
	vga_out8 (0x3d5, par->CR65);

	/* restore the desired video mode with cr67 */
	vga_out8 (0x3d4, 0x67);
	/* following part not present in X11 driver */
	cr67 = vga_in8 (0x3d5) & 0xf;
	vga_out8 (0x3d5, 0x50 | cr67);
	udelay (10000);
	vga_out8 (0x3d4, 0x67);
	/* end of part */
	vga_out8 (0x3d5, par->CR67 & ~0x0c);

	/* other mode timing and extended regs */
	vga_out8 (0x3d4, 0x34);
	vga_out8 (0x3d5, par->CR34);
	vga_out8 (0x3d4, 0x40);
	vga_out8 (0x3d5, par->CR40);
	vga_out8 (0x3d4, 0x42);
	vga_out8 (0x3d5, par->CR42);
	vga_out8 (0x3d4, 0x45);
	vga_out8 (0x3d5, par->CR45);
	vga_out8 (0x3d4, 0x50);
	vga_out8 (0x3d5, par->CR50);
	vga_out8 (0x3d4, 0x51);
	vga_out8 (0x3d5, par->CR51);

	/* memory timings */
	vga_out8 (0x3d4, 0x36);
	vga_out8 (0x3d5, par->CR36);
	vga_out8 (0x3d4, 0x60);
	vga_out8 (0x3d5, par->CR60);
	vga_out8 (0x3d4, 0x68);
	vga_out8 (0x3d5, par->CR68);
	vga_out8 (0x3d4, 0x69);
	vga_out8 (0x3d5, par->CR69);
	vga_out8 (0x3d4, 0x6f);
	vga_out8 (0x3d5, par->CR6F);

	vga_out8 (0x3d4, 0x33);
	vga_out8 (0x3d5, par->CR33);
	vga_out8 (0x3d4, 0x86);
	vga_out8 (0x3d5, par->CR86);
	vga_out8 (0x3d4, 0x88);
	vga_out8 (0x3d5, par->CR88);
	vga_out8 (0x3d4, 0x90);
	vga_out8 (0x3d5, par->CR90);
	vga_out8 (0x3d4, 0x91);
	vga_out8 (0x3d5, par->CR91);

	if (par->chip == S3_SAVAGE4) {
		vga_out8 (0x3d4, 0xb0);
		vga_out8 (0x3d5, par->CRB0);
	}

	vga_out8 (0x3d4, 0x32);
	vga_out8 (0x3d5, par->CR32);

	/* unlock extended seq regs */
	vga_out8 (0x3c4, 0x08);
	vga_out8 (0x3c5, 0x06);

	/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
	 * that we should leave the default SR10 and SR11 values there.
	 */
	if (par->SR10 != 255) {
		vga_out8 (0x3c4, 0x10);
		vga_out8 (0x3c5, par->SR10);
		vga_out8 (0x3c4, 0x11);
		vga_out8 (0x3c5, par->SR11);
	}

	/* restore extended seq regs for dclk */
	vga_out8 (0x3c4, 0x0e);
	vga_out8 (0x3c5, par->SR0E);
	vga_out8 (0x3c4, 0x0f);
	vga_out8 (0x3c5, par->SR0F);
	vga_out8 (0x3c4, 0x12);
	vga_out8 (0x3c5, par->SR12);
	vga_out8 (0x3c4, 0x13);
	vga_out8 (0x3c5, par->SR13);
	vga_out8 (0x3c4, 0x29);
	vga_out8 (0x3c5, par->SR29);

	vga_out8 (0x3c4, 0x18);
	vga_out8 (0x3c5, par->SR18);

	/* load new m, n pll values for dclk & mclk */
	vga_out8 (0x3c4, 0x15);
	tmp = vga_in8 (0x3c5) & ~0x21;

	vga_out8 (0x3c5, tmp | 0x03);
	vga_out8 (0x3c5, tmp | 0x23);
	vga_out8 (0x3c5, tmp | 0x03);
	vga_out8 (0x3c5, par->SR15);
	udelay (100);

	vga_out8 (0x3c4, 0x30);
	vga_out8 (0x3c5, par->SR30);
	vga_out8 (0x3c4, 0x08);
	vga_out8 (0x3c5, par->SR08);

	/* now write out cr67 in full, possibly starting STREAMS */
	VerticalRetraceWait();
	vga_out8 (0x3d4, 0x67);
	vga_out8 (0x3d5, par->CR67);

	vga_out8 (0x3d4, 0x66);
	cr66 = vga_in8 (0x3d5);
	vga_out8 (0x3d5, cr66 | 0x80);
	vga_out8 (0x3d4, 0x3a);
	cr3a = vga_in8 (0x3d5);
	vga_out8 (0x3d5, cr3a | 0x80);

	if (par->chip != S3_SAVAGE_MX) {
		VerticalRetraceWait();
		savage_out32 (FIFO_CONTROL_REG, par->MMPR0);
		par->SavageWaitIdle (par);
		savage_out32 (MIU_CONTROL_REG, par->MMPR1);
		par->SavageWaitIdle (par);
		savage_out32 (STREAMS_TIMEOUT_REG, par->MMPR2);
		par->SavageWaitIdle (par);
		savage_out32 (MISC_TIMEOUT_REG, par->MMPR3);
	}

	vga_out8 (0x3d4, 0x66);
	vga_out8 (0x3d5, cr66);
	vga_out8 (0x3d4, 0x3a);
	vga_out8 (0x3d5, cr3a);

	SavageSetup2DEngine (par);
	vgaHWProtect (par, 0);
}

static void savagefb_update_start (struct savagefb_par      *par,
				   struct fb_var_screeninfo *var)
{
	int base;

	base = ((var->yoffset * var->xres_virtual + (var->xoffset & ~1))
		* ((var->bits_per_pixel+7) / 8)) >> 2;

	/* now program the start address registers */
	vga_out16(0x3d4, (base & 0x00ff00) | 0x0c);
	vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d);
	vga_out8 (0x3d4, 0x69);
	vga_out8 (0x3d5, (base & 0x7f0000) >> 16);
}


static void savagefb_set_fix(struct fb_info *info)
{
	info->fix.line_length = info->var.xres_virtual *
		info->var.bits_per_pixel / 8;

	if (info->var.bits_per_pixel == 8)
		info->fix.visual      = FB_VISUAL_PSEUDOCOLOR;
	else
		info->fix.visual      = FB_VISUAL_TRUECOLOR;
}

#if defined(CONFIG_FB_SAVAGE_ACCEL)
static void savagefb_set_clip(struct fb_info *info)
{
    struct savagefb_par *par = (struct savagefb_par *)info->par;
    int cmd;

    cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
    par->bci_ptr = 0;
    par->SavageWaitFifo(par,3);
    BCI_SEND(cmd);
    BCI_SEND(BCI_CLIP_TL(0, 0));
    BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
}
#endif

static int savagefb_set_par (struct fb_info *info)
{
	struct savagefb_par *par = (struct savagefb_par *)info->par;
	struct fb_var_screeninfo *var = &info->var;
	int err;

	DBG("savagefb_set_par");
	err = savagefb_decode_var (var, par);
	if (err)
		return err;

	if (par->dacSpeedBpp <= 0) {
		if (var->bits_per_pixel > 24)
			par->dacSpeedBpp = par->clock[3];
		else if (var->bits_per_pixel >= 24)
			par->dacSpeedBpp = par->clock[2];
		else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
			par->dacSpeedBpp = par->clock[1];
		else if (var->bits_per_pixel <= 8)
			par->dacSpeedBpp = par->clock[0];
	}

	/* Set ramdac limits */
	par->maxClock = par->dacSpeedBpp;
	par->minClock = 10000;

	savagefb_set_par_int (par);
	savagefb_update_start (par, var);
	fb_set_cmap (&info->cmap, info);
	savagefb_set_fix(info);
	savagefb_set_clip(info);

	SavagePrintRegs();
	return 0;
}

/*
 *    Pan or Wrap the Display
 */
static int savagefb_pan_display (struct fb_var_screeninfo *var,
				 struct fb_info           *info)
{
	struct savagefb_par *par = (struct savagefb_par *)info->par;
	u_int y_bottom;

	y_bottom = var->yoffset;

	if (!(var->vmode & FB_VMODE_YWRAP))
		y_bottom += var->yres;

	if (var->xoffset > (var->xres_virtual - var->xres))
		return -EINVAL;
	if (y_bottom > info->var.yres_virtual)
		return -EINVAL;

	savagefb_update_start (par, var);

	info->var.xoffset = var->xoffset;
	info->var.yoffset = var->yoffset;

	if (var->vmode & FB_VMODE_YWRAP)
		info->var.vmode |= FB_VMODE_YWRAP;
	else
		info->var.vmode &= ~FB_VMODE_YWRAP;

	return 0;
}


static struct fb_ops savagefb_ops = {
	.owner          = THIS_MODULE,
	.fb_check_var   = savagefb_check_var,
	.fb_set_par     = savagefb_set_par,
	.fb_setcolreg   = savagefb_setcolreg,
	.fb_pan_display = savagefb_pan_display,
#if defined(CONFIG_FB_SAVAGE_ACCEL)
	.fb_fillrect    = savagefb_fillrect,
	.fb_copyarea    = savagefb_copyarea,
	.fb_imageblit   = savagefb_imageblit,
	.fb_sync        = savagefb_sync,
#else
	.fb_fillrect    = cfb_fillrect,
	.fb_copyarea    = cfb_copyarea,
	.fb_imageblit   = cfb_imageblit,
#endif
	.fb_cursor      = soft_cursor,
};

/* --------------------------------------------------------------------- */

static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = {
	.accel_flags =	FB_ACCELF_TEXT,
	.xres =		800,
	.yres =		600,
	.xres_virtual =  800,
	.yres_virtual =  600,
	.bits_per_pixel = 8,
	.pixclock =	25000,
	.left_margin =	88,
	.right_margin =	40,
	.upper_margin =	23,
	.lower_margin =	1,
	.hsync_len =	128,
	.vsync_len =	4,
	.sync =		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
	.vmode =	FB_VMODE_NONINTERLACED
};

static void savage_enable_mmio (struct savagefb_par *par)
{
	unsigned char val;

	DBG ("savage_enable_mmio\n");

	val = vga_in8 (0x3c3);
	vga_out8 (0x3c3, val | 0x01);
	val = vga_in8 (0x3cc);
	vga_out8 (0x3c2, val | 0x01);

	if (par->chip >= S3_SAVAGE4) {
		vga_out8 (0x3d4, 0x40);
		val = vga_in8 (0x3d5);
		vga_out8 (0x3d5, val | 1);
	}
}


void savage_disable_mmio (struct savagefb_par *par)
{
	unsigned char val;

	DBG ("savage_disable_mmio\n");

	if(par->chip >= S3_SAVAGE4 ) {
		vga_out8 (0x3d4, 0x40);
		val = vga_in8 (0x3d5);
		vga_out8 (0x3d5, val | 1);
	}
}


static int __devinit savage_map_mmio (struct fb_info *info)
{
	struct savagefb_par *par = (struct savagefb_par *)info->par;
	DBG ("savage_map_mmio");

	if (S3_SAVAGE3D_SERIES (par->chip))
		par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
			SAVAGE_NEWMMIO_REGBASE_S3;
	else
		par->mmio.pbase = pci_resource_start (par->pcidev, 0) +
			SAVAGE_NEWMMIO_REGBASE_S4;

	par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;

	par->mmio.vbase = ioremap (par->mmio.pbase, par->mmio.len);
	if (!par->mmio.vbase) {
		printk ("savagefb: unable to map memory mapped IO\n");
		return -ENOMEM;
	} else
		printk (KERN_INFO "savagefb: mapped io at %p\n",
			par->mmio.vbase);

	info->fix.mmio_start = par->mmio.pbase;
	info->fix.mmio_len   = par->mmio.len;

	par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
	par->bci_ptr  = 0;

	savage_enable_mmio (par);

	return 0;
}

static void __devinit savage_unmap_mmio (struct fb_info *info)
{
	struct savagefb_par *par = (struct savagefb_par *)info->par;
	DBG ("savage_unmap_mmio");

	savage_disable_mmio(par);

	if (par->mmio.vbase) {
		iounmap ((void __iomem *)par->mmio.vbase);
		par->mmio.vbase = NULL;
	}
}

static int __devinit savage_map_video (struct fb_info *info,
				       int video_len)
{
	struct savagefb_par *par = (struct savagefb_par *)info->par;
	int resource;

	DBG("savage_map_video");

	if (S3_SAVAGE3D_SERIES (par->chip))
		resource = 0;
	else
		resource = 1;

	par->video.pbase = pci_resource_start (par->pcidev, resource);
	par->video.len   = video_len;
	par->video.vbase = ioremap (par->video.pbase, par->video.len);

	if (!par->video.vbase) {
		printk ("savagefb: unable to map screen memory\n");
		return -ENOMEM;
	} else
		printk (KERN_INFO "savagefb: mapped framebuffer at %p, "
			"pbase == %x\n", par->video.vbase, par->video.pbase);

	info->fix.smem_start = par->video.pbase;
	info->fix.smem_len   = par->video.len - par->cob_size;
	info->screen_base    = par->video.vbase;

#ifdef CONFIG_MTRR
	par->video.mtrr = mtrr_add (par->video.pbase, video_len,
				     MTRR_TYPE_WRCOMB, 1);
#endif
	return 0;
}

static void __devinit savage_unmap_video (struct fb_info *info)
{
	struct savagefb_par *par = (struct savagefb_par *)info->par;

	DBG("savage_unmap_video");

	if (par->video.vbase) {
#ifdef CONFIG_MTRR
		mtrr_del (par->video.mtrr, par->video.pbase, par->video.len);
#endif

		iounmap (par->video.vbase);
		par->video.vbase = NULL;
		info->screen_base = NULL;
	}
}

static int __devinit savage_init_hw (struct savagefb_par *par)
{
	unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;

	static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
	static unsigned char RamSavage4[] =  { 2, 4, 8, 12, 16, 32, 64, 32 };
	static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
	static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };

	int videoRam, videoRambytes;

	DBG("savage_init_hw");

	/* unprotect CRTC[0-7] */
	vga_out8(0x3d4, 0x11);
	tmp = vga_in8(0x3d5);
	vga_out8(0x3d5, tmp & 0x7f);

	/* unlock extended regs */
	vga_out16(0x3d4, 0x4838);
	vga_out16(0x3d4, 0xa039);
	vga_out16(0x3c4, 0x0608);

	vga_out8(0x3d4, 0x40);
	tmp = vga_in8(0x3d5);
	vga_out8(0x3d5, tmp & ~0x01);

	/* unlock sys regs */
	vga_out8(0x3d4, 0x38);
	vga_out8(0x3d5, 0x48);

	/* Unlock system registers. */
	vga_out16(0x3d4, 0x4838);

	/* Next go on to detect amount of installed ram */

	vga_out8(0x3d4, 0x36);            /* for register CR36 (CONFG_REG1), */
	config1 = vga_in8(0x3d5);           /* get amount of vram installed */

	/* Compute the amount of video memory and offscreen memory. */

	switch  (par->chip) {
	case S3_SAVAGE3D:
		videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024;
		break;

	case S3_SAVAGE4:
		/*
		 * The Savage4 has one ugly special case to consider.  On
		 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
		 * when it really means 8MB.  Why do it the same when you
		 * can do it different...
		 */
		vga_out8(0x3d4, 0x68);	/* memory control 1 */
		if( (vga_in8(0x3d5) & 0xC0) == (0x01 << 6) )
			RamSavage4[1] = 8;

		/*FALLTHROUGH*/

	case S3_SAVAGE2000:
		videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024;
		break;

	case S3_SAVAGE_MX:
	case S3_SUPERSAVAGE:
		videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024;
		break;

	case S3_PROSAVAGE:
		videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024;
		break;

	default:
		/* How did we get here? */
		videoRam = 0;
		break;
	}

	videoRambytes = videoRam * 1024;

	printk (KERN_INFO "savagefb: probed videoram:  %dk\n", videoRam);

	/* reset graphics engine to avoid memory corruption */
	vga_out8 (0x3d4, 0x66);
	cr66 = vga_in8 (0x3d5);
	vga_out8 (0x3d5, cr66 | 0x02);
	udelay (10000);

	vga_out8 (0x3d4, 0x66);
	vga_out8 (0x3d5, cr66 & ~0x02);	/* clear reset flag */
	udelay (10000);


	/*
	 * reset memory interface, 3D engine, AGP master, PCI master,
	 * master engine unit, motion compensation/LPB
	 */
	vga_out8 (0x3d4, 0x3f);
	cr3f = vga_in8 (0x3d5);
	vga_out8 (0x3d5, cr3f | 0x08);
	udelay (10000);

	vga_out8 (0x3d4, 0x3f);
	vga_out8 (0x3d5, cr3f & ~0x08);	/* clear reset flags */
	udelay (10000);

	/* Savage ramdac speeds */
	par->numClocks = 4;
	par->clock[0] = 250000;
	par->clock[1] = 250000;
	par->clock[2] = 220000;
	par->clock[3] = 220000;

	/* detect current mclk */
	vga_out8(0x3c4, 0x08);
	sr8 = vga_in8(0x3c5);
	vga_out8(0x3c5, 0x06);
	vga_out8(0x3c4, 0x10);
	n = vga_in8(0x3c5);
	vga_out8(0x3c4, 0x11);
	m = vga_in8(0x3c5);
	vga_out8(0x3c4, 0x08);
	vga_out8(0x3c5, sr8);
	m &= 0x7f;
	n1 = n & 0x1f;
	n2 = (n >> 5) & 0x03;
	par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
	printk (KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
		par->MCLK);

	/* Check LCD panel parrmation */

	if (par->chip == S3_SAVAGE_MX) {
		unsigned char cr6b = VGArCR( 0x6b );

		int panelX = (VGArSEQ (0x61) +
			      ((VGArSEQ (0x66) & 0x02) << 7) + 1) * 8;