📄 skdrv2nd.h
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TXD *pNextTxd; /* Pointer to next Txd */ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */};/* Used interrupt bits in the interrupts source register *********************/#define DRIVER_IRQS ((IS_IRQ_SW) | \ (IS_R1_F) |(IS_R2_F) | \ (IS_XS1_F) |(IS_XA1_F) | \ (IS_XS2_F) |(IS_XA2_F))#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \ (IS_EXT_REG) |(IS_TIMINT) | \ (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \ (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \ (IS_MAC1) |(IS_LNK_SYNC_M1)| \ (IS_MAC2) |(IS_LNK_SYNC_M2)| \ (IS_R1_C) |(IS_R2_C) | \ (IS_XS1_C) |(IS_XA1_C) | \ (IS_XS2_C) |(IS_XA2_C))#define IRQ_MASK ((IS_IRQ_SW) | \ (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \ (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \ (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \ (IS_HW_ERR) |(IS_I2C_READY)| \ (IS_EXT_REG) |(IS_TIMINT) | \ (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \ (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \ (IS_MAC1) |(IS_MAC2) | \ (IS_R1_C) |(IS_R2_C) | \ (IS_XS1_C) |(IS_XA1_C) | \ (IS_XS2_C) |(IS_XA2_C))#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */typedef struct s_DevNet DEV_NET;struct s_DevNet { int PortNr; int NetNr; int Mtu; int Up; SK_AC *pAC;}; typedef struct s_TxPort TX_PORT;struct s_TxPort { /* the transmit descriptor rings */ caddr_t pTxDescrRing; /* descriptor area memory */ SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */ TXD *pTxdRingHead; /* Head of Tx rings */ TXD *pTxdRingTail; /* Tail of Tx rings */ TXD *pTxdRingPrev; /* descriptor sent previously */ int TxdRingFree; /* # of free entrys */ spinlock_t TxDesRingLock; /* serialize descriptor accesses */ SK_IOC HwAddr; /* bmu registers address */ int PortIndex; /* index number of port (0 or 1) */};typedef struct s_RxPort RX_PORT;struct s_RxPort { /* the receive descriptor rings */ caddr_t pRxDescrRing; /* descriptor area memory */ SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */ RXD *pRxdRingHead; /* Head of Rx rings */ RXD *pRxdRingTail; /* Tail of Rx rings */ RXD *pRxdRingPrev; /* descriptor given to BMU previously */ int RxdRingFree; /* # of free entrys */ spinlock_t RxDesRingLock; /* serialize descriptor accesses */ int RxFillLimit; /* limit for buffers in ring */ SK_IOC HwAddr; /* bmu registers address */ int PortIndex; /* index number of port (0 or 1) */};/* Definitions needed for interrupt moderation *******************************/#define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))#define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))#define IRQ_MASK_TX_ONLY ((IRQ_EOF_AS_TX)| (IRQ_EOF_SY_TX))#define IRQ_MASK_RX_ONLY ((IS_R1_F) | (IS_R2_F))#define IRQ_MASK_SP_ONLY (SPECIAL_IRQS)#define IRQ_MASK_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))#define IRQ_MASK_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))#define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))#define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))#define C_INT_MOD_NONE 1#define C_INT_MOD_STATIC 2#define C_INT_MOD_DYNAMIC 4#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */#define C_INTS_PER_SEC_DEFAULT 2000 #define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */#define C_INT_MOD_IPS_LOWER_RANGE 30#define C_INT_MOD_IPS_UPPER_RANGE 40000typedef struct s_DynIrqModInfo DIM_INFO;struct s_DynIrqModInfo { unsigned long PrevTimeVal; unsigned int PrevSysLoad; unsigned int PrevUsedTime; unsigned int PrevTotalTime; int PrevUsedDescrRatio; int NbrProcessedDescr; SK_U64 PrevPort0RxIntrCts; SK_U64 PrevPort1RxIntrCts; SK_U64 PrevPort0TxIntrCts; SK_U64 PrevPort1TxIntrCts; SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */ int MaxModIntsPerSec; /* Moderation Threshold */ int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */ int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */ long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */ SK_BOOL DisplayStats; /* Stats yes/no */ SK_BOOL AutoSizing; /* Resize DIM-timer on/off */ int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */ SK_TIMER ModTimer; /* just some timer */};typedef struct s_PerStrm PER_STRM;#define SK_ALLOC_IRQ 0x00000001#ifdef SK_DIAG_SUPPORT#define DIAG_ACTIVE 1#define DIAG_NOTACTIVE 0#endif/**************************************************************************** * Per board structure / Adapter Context structure: * Allocated within attach(9e) and freed within detach(9e). * Contains all 'per device' necessary handles, flags, locks etc.: */struct s_AC { SK_GEINIT GIni; /* GE init struct */ SK_PNMI Pnmi; /* PNMI data struct */ SK_VPD vpd; /* vpd data struct */ SK_QUEUE Event; /* Event queue */ SK_HWT Hwt; /* Hardware Timer control struct */ SK_TIMCTRL Tim; /* Software Timer control struct */ SK_I2C I2c; /* I2C relevant data structure */ SK_ADDR Addr; /* for Address module */ SK_CSUM Csum; /* for checksum module */ SK_RLMT Rlmt; /* for rlmt module */ spinlock_t SlowPathLock; /* Normal IRQ lock */ struct timer_list BlinkTimer; /* for LED blinking */ int LedsOn; SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */ int RlmtMode; /* link check mode to set */ int RlmtNets; /* Number of nets */ SK_IOC IoBase; /* register set of adapter */ int BoardLevel; /* level of active hw init (0-2) */ char DeviceStr[80]; /* adapter string from vpd */ SK_U32 AllocFlag; /* flag allocation of resources */ struct pci_dev *PciDev; /* for access to pci config space */ SK_U32 PciDevId; /* pci device id */ struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */ char Name[30]; /* driver name */ int RxBufSize; /* length of receive buffers */ struct net_device_stats stats; /* linux 'netstat -i' statistics */ int Index; /* internal board index number */ /* adapter RAM sizes for queues of active port */ int RxQueueSize; /* memory used for receive queue */ int TxSQueueSize; /* memory used for sync. tx queue */ int TxAQueueSize; /* memory used for async. tx queue */ int PromiscCount; /* promiscuous mode counter */ int AllMultiCount; /* allmulticast mode counter */ int MulticCount; /* number of different MC */ /* addresses for this board */ /* (may be more than HW can)*/ int HWRevision; /* Hardware revision */ int ActivePort; /* the active XMAC port */ int MaxPorts; /* number of activated ports */ int TxDescrPerRing; /* # of descriptors per tx ring */ int RxDescrPerRing; /* # of descriptors per rx ring */ caddr_t pDescrMem; /* Pointer to the descriptor area */ dma_addr_t pDescrMemDMA; /* PCI DMA address of area */ /* the port structures with descriptor rings */ TX_PORT TxPort[SK_MAX_MACS][2]; RX_PORT RxPort[SK_MAX_MACS]; unsigned int CsOfs1; /* for checksum calculation */ unsigned int CsOfs2; /* for checksum calculation */ SK_U32 CsOfs; /* for checksum calculation */ SK_BOOL CheckQueue; /* check event queue soon */ SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */ DIM_INFO DynIrqModInfo; /* all data related to DIM */ /* Only for tests */ int PortUp; int PortDown; int ChipsetType; /* Chipset family type * 0 == Genesis family support * 1 == Yukon family support */#ifdef SK_DIAG_SUPPORT SK_U32 DiagModeActive; /* is diag active? */ SK_BOOL DiagFlowCtrl; /* for control purposes */ SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */ SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while * DIAG is busy with NIC */#endif};#endif /* __INC_SKDRV2ND_H */
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