supern_2.h

h内核

/*
 *  PLC read/write (r/w) registers
 */
#define PL_CNTRL_A	0x00		/* control register A (r/w) */
#define PL_CNTRL_B	0x01		/* control register B (r/w) */
#define PL_INTR_MASK	0x02		/* interrupt mask (r/w) */
#define PL_XMIT_VECTOR	0x03		/* transmit vector register (r/w) */
#define PL_VECTOR_LEN	0x04		/* transmit vector length (r/w) */
#define PL_LE_THRESHOLD	0x05		/* link error event threshold (r/w) */
#define PL_C_MIN	0x06		/* minimum connect state time (r/w) */
#define PL_TL_MIN	0x07		/* min. line state transmit t. (r/w) */
#define PL_TB_MIN	0x08		/* minimum break time (r/w) */
#define PL_T_OUT	0x09		/* signal timeout (r/w) */
#define PL_CNTRL_C	0x0a		/* control register C (r/w) */
#define PL_LC_LENGTH	0x0b		/* link confidence test time (r/w) */
#define PL_T_SCRUB	0x0c		/* scrub time = MAC TVX (r/w) */
#define PL_NS_MAX	0x0d		/* max. noise time before break (r/w)*/
#define PL_TPC_LOAD_V	0x0e		/* TPC timer load value (write only) */
#define PL_TNE_LOAD_V	0x0f		/* TNE timer load value (write only) */
#define PL_STATUS_A	0x10		/* status register A (read only) */
#define PL_STATUS_B	0x11		/* status register B (read only) */
#define PL_TPC		0x12		/* timer for PCM (ro) [20.48 us] */
#define PL_TNE		0x13		/* time of noise event [0.32 us] */
#define PL_CLK_DIV	0x14		/* TNE clock divider (read only) */
#define PL_BIST_SIGNAT	0x15		/* built in self test signature (ro)*/
#define PL_RCV_VECTOR	0x16		/* receive vector reg. (read only) */
#define PL_INTR_EVENT	0x17		/* interrupt event reg. (read only) */
#define PL_VIOL_SYM_CTR	0x18		/* violation symbol count. (read o) */
#define PL_MIN_IDLE_CTR	0x19		/* minimum idle counter (read only) */
#define PL_LINK_ERR_CTR	0x1a		/* link error event ctr.(read only) */
#ifdef	MOT_ELM
#define	PL_T_FOT_ASS	0x1e		/* FOTOFF Assert Timer */
#define	PL_T_FOT_DEASS	0x1f		/* FOTOFF Deassert Timer */
#endif	/* MOT_ELM */

#ifdef	MOT_ELM
/*
 * Special Quad-Elm Registers.
 * A Quad-ELM consists of for ELMs and these additional registers.
 */
#define	QELM_XBAR_W	0x80		/* Crossbar Control ELM W */
#define	QELM_XBAR_X	0x81		/* Crossbar Control ELM X */
#define	QELM_XBAR_Y	0x82		/* Crossbar Control ELM Y */
#define	QELM_XBAR_Z	0x83		/* Crossbar Control ELM Z */
#define	QELM_XBAR_P	0x84		/* Crossbar Control Bus P */
#define	QELM_XBAR_S	0x85		/* Crossbar Control Bus S */
#define	QELM_XBAR_R	0x86		/* Crossbar Control Bus R */
#define	QELM_WR_XBAR	0x87		/* Write the Crossbar now (write) */
#define	QELM_CTR_W	0x88		/* Counter W */
#define	QELM_CTR_X	0x89		/* Counter X */
#define	QELM_CTR_Y	0x8a		/* Counter Y */
#define	QELM_CTR_Z	0x8b		/* Counter Z */
#define	QELM_INT_MASK	0x8c		/* Interrupt mask register */
#define	QELM_INT_DATA	0x8d		/* Interrupt data (event) register */
#define	QELM_ELMB	0x00		/* Elm base */
#define	QELM_ELM_SIZE	0x20		/* ELM size */
#endif	/* MOT_ELM */
/*
 * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
 * It is used for timer configuration, specification of PCM MAINT state option,
 * counter interrupt frequency, PLC data path config. and Built In Self Test.
 */
#define	PL_RUN_BIST	0x0001		/* begin running its Built In Self T.*/
#define	PL_RF_DISABLE	0x0002		/* disable the Repeat Filter state m.*/
#define	PL_SC_REM_LOOP	0x0004		/* remote loopback path */
#define	PL_SC_BYPASS	0x0008		/* by providing a physical bypass */
#define	PL_LM_LOC_LOOP	0x0010		/* loop path just after elastic buff.*/
#define	PL_EB_LOC_LOOP	0x0020		/* loop path just prior to PDT/PDR IF*/
#define	PL_FOT_OFF	0x0040		/* assertion of /FOTOFF pin of PLC */
#define	PL_LOOPBACK	0x0080		/* it cause the /LPBCK pin ass. low */
#define	PL_MINI_CTR_INT 0x0100		/* partially contr. when bit is ass. */
#define	PL_VSYM_CTR_INT	0x0200		/* controls when int bit is asserted */
#define	PL_ENA_PAR_CHK	0x0400		/* enable parity check */
#define	PL_REQ_SCRUB	0x0800		/* limited access to scrub capability*/
#define	PL_TPC_16BIT	0x1000		/* causes the TPC as a 16 bit timer */
#define	PL_TNE_16BIT	0x2000		/* causes the TNE as a 16 bit timer */
#define	PL_NOISE_TIMER	0x4000		/* allows the noise timing function */

/*
 * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
 * It contains signals and requeste to direct the process of PCM and it is also
 * used to control the Line State Match interrupt.
 */
#define	PL_PCM_CNTRL	0x0003		/* control PCM state machine */
#define	PL_PCM_NAF	(0)		/* state is not affected */
#define	PL_PCM_START	(1)		/* goes to the BREAK state */
#define	PL_PCM_TRACE	(2)		/* goes to the TRACE state */
#define	PL_PCM_STOP	(3)		/* goes to the OFF state */

#define	PL_MAINT	0x0004		/* if OFF state --> MAINT state */
#define	PL_LONG		0x0008		/* perf. a long Link Confid.Test(LCT)*/
#define	PL_PC_JOIN	0x0010		/* if NEXT state --> JOIN state */

#define	PL_PC_LOOP	0x0060		/* loopback used in the LCT */
#define	PL_NOLCT	(0<<5)		/* no LCT is performed */
#define	PL_TPDR		(1<<5)		/* PCM asserts transmit PDR */
#define	PL_TIDLE	(2<<5)		/* PCM asserts transmit idle */
#define	PL_RLBP		(3<<5)		/* trans. PDR & remote loopb. path */

#define	PL_CLASS_S	0x0080		/* signif. that single att. station */

#define	PL_MAINT_LS	0x0700		/* line state while in the MAINT st. */
#define	PL_M_QUI0	(0<<8)		/* transmit QUIET line state */
#define	PL_M_IDLE	(1<<8)		/* transmit IDLE line state */
#define	PL_M_HALT	(2<<8)		/* transmit HALT line state */
#define	PL_M_MASTR	(3<<8)		/* transmit MASTER line state */
#define	PL_M_QUI1	(4<<8)		/* transmit QUIET line state */
#define	PL_M_QUI2	(5<<8)		/* transmit QUIET line state */
#define	PL_M_TPDR	(6<<8)		/* tr. PHY_DATA requ.-symbol is tr.ed*/
#define	PL_M_QUI3	(7<<8)		/* transmit QUIET line state */

#define	PL_MATCH_LS	0x7800		/* line state to be comp. with curr.*/
#define	PL_I_ANY	(0<<11)		/* Int. on any change in *_LINE_ST */
#define	PL_I_IDLE	(1<<11)		/* Interrupt on IDLE line state */
#define	PL_I_HALT	(2<<11)		/* Interrupt on HALT line state */
#define	PL_I_MASTR	(4<<11)		/* Interrupt on MASTER line state */
#define	PL_I_QUIET	(8<<11)		/* Interrupt on QUIET line state */

#define	PL_CONFIG_CNTRL	0x8000		/* control over scrub, byp. & loopb.*/

/*
 * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
 * It contains the scrambling control registers (PLC-S only)
 */
#define PL_C_CIPHER_ENABLE	(1<<0)	/* enable scrambler */
#define PL_C_CIPHER_LPBCK	(1<<1)	/* loopback scrambler */
#define PL_C_SDOFF_ENABLE	(1<<6)	/* enable SDOFF timer */
#define PL_C_SDON_ENABLE	(1<<7)	/* enable SDON timer */
#ifdef	MOT_ELM
#define PL_C_FOTOFF_CTRL	(3<<2)	/* FOTOFF timer control */
#define PL_C_FOTOFF_TIM		(0<<2)	/* FOTOFF use timer for (de)-assert */
#define PL_C_FOTOFF_INA		(2<<2)	/* FOTOFF forced inactive */
#define PL_C_FOTOFF_ACT		(3<<2)	/* FOTOFF forced active */
#define PL_C_FOTOFF_SRCE	(1<<4)	/* FOTOFF source is PCM state != OFF */
#define	PL_C_RXDATA_EN		(1<<5)	/* Rec scr data forced to 0 */
#define	PL_C_SDNRZEN		(1<<8)	/* Monitor rec descr. data for act */
#else	/* nMOT_ELM */
#define PL_C_FOTOFF_CTRL	(3<<8)	/* FOTOFF timer control */
#define PL_C_FOTOFF_0		(0<<8)	/* timer off */
#define PL_C_FOTOFF_30		(1<<8)	/* 30uS */
#define PL_C_FOTOFF_50		(2<<8)	/* 50uS */
#define PL_C_FOTOFF_NEVER	(3<<8)	/* never */
#define PL_C_SDON_TIMER		(3<<10)	/* SDON timer control */
#define PL_C_SDON_084		(0<<10)	/* 0.84 uS */
#define PL_C_SDON_132		(1<<10)	/* 1.32 uS */
#define PL_C_SDON_252		(2<<10)	/* 2.52 uS */
#define PL_C_SDON_512		(3<<10)	/* 5.12 uS */
#define PL_C_SOFF_TIMER		(3<<12)	/* SDOFF timer control */
#define PL_C_SOFF_076		(0<<12)	/* 0.76 uS */
#define PL_C_SOFF_132		(1<<12)	/* 1.32 uS */
#define PL_C_SOFF_252		(2<<12)	/* 2.52 uS */
#define PL_C_SOFF_512		(3<<12)	/* 5.12 uS */
#define PL_C_TSEL		(3<<14)	/* scrambler path select */
#endif	/* nMOT_ELM */

/*
 * PLC status register A (PL_STATUS_A: log. addr. 0x10)
 * It is used to report status information to the Node Processor about the 
 * Line State Machine (LSM).
 */
#ifdef	MOT_ELM
#define PLC_INT_MASK	0xc000		/* ELM integration bits in status A */
#define PLC_INT_C	0x0000		/* ELM Revision Band C */
#define PLC_INT_CAMEL	0x4000		/* ELM integrated into CAMEL */
#define PLC_INT_QE	0x8000		/* ELM integrated into Quad ELM */
#define PLC_REV_MASK	0x3800		/* revision bits in status A */
#define PLC_REVISION_B	0x0000		/* rev bits for ELM Rev B */
#define PLC_REVISION_QA	0x0800		/* rev bits for ELM core in QELM-A */
#else	/* nMOT_ELM */
#define PLC_REV_MASK	0xf800		/* revision bits in status A */
#define PLC_REVISION_A	0x0000		/* revision bits for PLC */
#define PLC_REVISION_S	0xf800		/* revision bits for PLC-S */
#define PLC_REV_SN3	0x7800		/* revision bits for PLC-S in IFCP */
#endif	/* nMOT_ELM */
#define	PL_SYM_PR_CTR	0x0007		/* contains the LSM symbol pair Ctr. */
#define	PL_UNKN_LINE_ST	0x0008		/* unknown line state bit from LSM */
#define	PL_LSM_STATE	0x0010		/* state bit of LSM */

#define	PL_LINE_ST	0x00e0		/* contains recogn. line state of LSM*/
#define	PL_L_NLS	(0<<5)		/* noise line state */
#define	PL_L_ALS	(1<<5)		/* activ line state */
#define	PL_L_UND	(2<<5)		/* undefined */
#define	PL_L_ILS4	(3<<5)		/* idle l. s. (after 4 idle symbols) */
#define	PL_L_QLS	(4<<5)		/* quiet line state */
#define	PL_L_MLS	(5<<5)		/* master line state */
#define	PL_L_HLS	(6<<5)		/* halt line state */
#define	PL_L_ILS16	(7<<5)		/* idle line state (after 16 idle s.)*/

#define	PL_PREV_LINE_ST	0x0300		/* value of previous line state */
#define	PL_P_QLS	(0<<8)		/* quiet line state */
#define	PL_P_MLS	(1<<8)		/* master line state */
#define	PL_P_HLS	(2<<8)		/* halt line state */
#define	PL_P_ILS16	(3<<8)		/* idle line state (after 16 idle s.)*/

#define	PL_SIGNAL_DET	0x0400		/* 1=that signal detect is deasserted*/


/*
 * PLC status register B (PL_STATUS_B: log. addr. 0x11)
 * It contains signals and status from the repeat filter and PCM state machine.
 */
#define	PL_BREAK_REASON	0x0007		/* reason for PCM state mach.s to br.*/
#define	PL_B_NOT	(0)		/* PCM SM has not gone to BREAK state*/
#define	PL_B_PCS	(1)		/* PC_Start issued */
#define	PL_B_TPC	(2)		/* TPC timer expired after T_OUT */
#define	PL_B_TNE	(3)		/* TNE timer expired after NS_MAX */
#define	PL_B_QLS	(4)		/* quit line state detected */
#define	PL_B_ILS	(5)		/* idle line state detected */
#define	PL_B_HLS	(6)		/* halt line state detected */

#define	PL_TCF		0x0008		/* transmit code flag (start exec.) */
#define	PL_RCF		0x0010		/* receive code flag (start exec.) */
#define	PL_LSF		0x0020		/* line state flag (l.s. has been r.)*/
#define	PL_PCM_SIGNAL	0x0040		/* indic. that XMIT_VECTOR hb.written*/

#define	PL_PCM_STATE	0x0780		/* state bits of PCM state machine */
#define	PL_PC0		(0<<7)		/* OFF	   - when /RST or PCM_CNTRL */
#define	PL_PC1		(1<<7)		/* BREAK   - entry point in start PCM*/
#define	PL_PC2		(2<<7)		/* TRACE   - to localize stuck Beacon*/
#define	PL_PC3		(3<<7)		/* CONNECT - synchronize ends of conn*/
#define	PL_PC4		(4<<7)		/* NEXT	   - to separate the signalng*/
#define	PL_PC5		(5<<7)		/* SIGNAL  - PCM trans/rec. bit infos*/
#define	PL_PC6		(6<<7)		/* JOIN	   - 1. state to activ conn. */
#define	PL_PC7		(7<<7)		/* VERIFY  - 2. - " - (3. ACTIVE) */
#define	PL_PC8		(8<<7)		/* ACTIVE  - PHY has been incorporated*/
#define	PL_PC9		(9<<7)		/* MAINT   - for test purposes or so 
					   that PCM op. completely in softw. */

#define	PL_PCI_SCRUB	0x0800		/* scrubbing function is being exec. */

#define	PL_PCI_STATE	0x3000		/* Physical Connect. Insertion SM */
#define	PL_CI_REMV	(0<<12)		/* REMOVED */
#define	PL_CI_ISCR	(1<<12)		/* INSERT_SCRUB */
#define	PL_CI_RSCR	(2<<12)		/* REMOVE_SCRUB */
#define	PL_CI_INS	(3<<12)		/* INSERTED */

#define	PL_RF_STATE	0xc000		/* state bit of repeate filter SM */
#define	PL_RF_REPT	(0<<14)		/* REPEAT */
#define	PL_RF_IDLE	(1<<14)		/* IDLE */
#define	PL_RF_HALT1	(2<<14)		/* HALT1 */
#define	PL_RF_HALT2	(3<<14)		/* HALT2 */


/*
 * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17)
 * It is read only and is clearde whenever it is read!
 * It is used by the PLC to report events to the node processor.
 */
#define	PL_PARITY_ERR	0x0001		/* p. error h.b.detected on TX9-0 inp*/
#define	PL_LS_MATCH	0x0002		/* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/
#define	PL_PCM_CODE	0x0004		/* transmit&receive | LCT complete */
#define	PL_TRACE_PROP	0x0008		/* master l.s. while PCM ACTIV|TRACE */
#define	PL_SELF_TEST	0x0010		/* QUIET|HALT while PCM in TRACE st. */
#define	PL_PCM_BREAK	0x0020		/* PCM has entered the BREAK state */
#define	PL_PCM_ENABLED	0x0040		/* asserted SC_JOIN, scrub. & ACTIV */
#define	PL_TPC_EXPIRED	0x0080		/* TPC timer reached zero */
#define	PL_TNE_EXPIRED	0x0100		/* TNE timer reached zero */
#define	PL_EBUF_ERR	0x0200		/* elastic buff. det. over-|underflow*/
#define	PL_PHYINV	0x0400		/* physical layer invalid signal */
#define	PL_VSYM_CTR	0x0800		/* violation symbol counter has incr.*/
#define	PL_MINI_CTR	0x1000		/* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
#define	PL_LE_CTR	0x2000		/* link error event counter */
#define	PL_LSDO		0x4000		/* SDO input pin changed to a 1 */
#define	PL_NP_ERR	0x8000		/* NP has requested to r/w an inv. r.*/

/*
 * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is
 * equal PL_INTR_EVENT register.
 * For each set bit, the setting of corresponding bit generate an int to NP. 
 */

#ifdef	MOT_ELM
/*
 * Quad ELM Crosbar Control register values (QELM_XBAR_?)
 */
#define	QELM_XOUT_IDLE	0x0000		/* Idles/Passthrough */
#define	QELM_XOUT_P	0x0001		/* Output to: Bus P */
#define	QELM_XOUT_S	0x0002		/* Output to: Bus S */
#define	QELM_XOUT_R	0x0003		/* Output to: Bus R */
#define	QELM_XOUT_W	0x0004		/* Output to: ELM W */
#define	QELM_XOUT_X	0x0005		/* Output to: ELM X */
#define	QELM_XOUT_Y	0x0006		/* Output to: ELM Y */
#define	QELM_XOUT_Z	0x0007		/* Output to: ELM Z */

/*
 * Quad ELM Interrupt data and event registers.
 */
#define	QELM_NP_ERR	(1<<15)		/* Node Processor Error */
#define	QELM_COUNT_Z	(1<<7)		/* Counter Z Interrupt */
#define	QELM_COUNT_Y	(1<<6)		/* Counter Y Interrupt */
#define	QELM_COUNT_X	(1<<5)		/* Counter X Interrupt */
#define	QELM_COUNT_W	(1<<4)		/* Counter W Interrupt */
#define	QELM_ELM_Z	(1<<3)		/* ELM Z Interrupt */
#define	QELM_ELM_Y	(1<<2)		/* ELM Y Interrupt */
#define	QELM_ELM_X	(1<<1)		/* ELM X Interrupt */
#define	QELM_ELM_W	(1<<0)		/* ELM W Interrupt */
#endif	/* MOT_ELM */
/*
 * PLC Timing Parameters
 */
#define	TP_C_MIN	0xff9c	/*   2    ms */
#define	TP_TL_MIN	0xfff0	/*   0.3  ms */
#define	TP_TB_MIN	0xff10	/*   5    ms */
#define	TP_T_OUT	0xd9db	/* 200    ms */
#define	TP_LC_LENGTH	0xf676	/*  50    ms */
#define	TP_LC_LONGLN	0xa0a2	/* 500    ms */
#define	TP_T_SCRUB	0xff6d	/*   3.5  ms */
#define	TP_NS_MAX	0xf021	/*   1.3   ms */

/*
 * BIST values
 */
#define PLC_BIST	0x6ecd		/* BIST signature for PLC */
#define PLCS_BIST	0x5b6b 		/* BIST signature for PLC-S */
#define	PLC_ELM_B_BIST	0x6ecd		/* BIST signature of ELM Rev. B */
#define	PLC_ELM_D_BIST	0x5b6b		/* BIST signature of ELM Rev. D */
#define	PLC_CAM_A_BIST	0x9e75		/* BIST signature of CAMEL Rev. A */
#define	PLC_CAM_B_BIST	0x5b6b		/* BIST signature of CAMEL Rev. B */
#define	PLC_IFD_A_BIST	0x9e75		/* BIST signature of IFDDI Rev. A */
#define	PLC_IFD_B_BIST	0x5b6b		/* BIST signature of IFDDI Rev. B */
#define	PLC_QELM_A_BIST	0x5b6b		/* BIST signature of QELM Rev. A */

/*
 	FDDI board recources	
 */

/*
 * request register array (log. addr: RQA_A + a<<1 {a=0..7}) write only.
 * It specifies to FORMAC+ the type of buffer memory access the host requires.
 */
#define	RQ_NOT		0		/* not request */
#define	RQ_RES		1		/* reserved */
#define	RQ_SFW		2		/* special frame write */
#define	RQ_RRQ		3		/* read request: receive queue */
#define	RQ_WSQ		4		/* write request: synchronous queue */
#define	RQ_WA0		5		/* write requ.: asynchronous queue 0 */
#define	RQ_WA1		6		/* write requ.: asynchronous queue 1 */
#define	RQ_WA2		7		/* write requ.: asynchronous queue 2 */

#define	SZ_LONG		(sizeof(long))

/*
 * FDDI defaults
 * NOTE : In the ANSI docs, times are specified in units of "symbol time".
 * 	  AMD chips use BCLK as unit. 1 BCKL == 2 symbols
 */
#define	COMPLREF	((u_long)32*256*256)	/* two's complement 21 bit */
#define MSTOBCLK(x)	((u_long)(x)*12500L)
#define MSTOTVX(x)	(((u_long)(x)*1000L)/80/255)

#endif	/* _SUPERNET_ */