supern_2.h

h内核

#define	FM_AFMASK2	0xbc		/* r/w Address Filter Mask 2 */
#define	FM_AFMASK1	0xbe		/* r/w Address Filter Mask 1 */
#define	FM_AFMASK0	0xc0		/* r/w Address Filter Mask 0 */
#define	FM_AFPERS	0xc2		/* r/w Address Filter Personality Reg */

/* Supernet 3: Orion (PDX?) Registers */
#define	FM_ORBIST	0xd0		/* r/w Orion BIST signature */
#define	FM_ORSTAT	0xd2		/* r/w Orion Status Register */


/*
 * Mode Register 1 (MDREG1)
 */
#define FM_RES0		0x0001		/* reserved */
					/* SN3: other definition */
#define	FM_XMTINH_HOLD	0x0002		/* transmit-inhibit/hold bit */
					/* SN3: other definition */
#define	FM_HOFLXI	0x0003		/* SN3: Hold / Flush / Inhibit */
#define	FM_FULL_HALF	0x0004		/* full-duplex/half-duplex bit */
#define	FM_LOCKTX	0x0008		/* lock-transmit-asynchr.-queues bit */
#define FM_EXGPA0	0x0010		/* extended-group-addressing bit 0 */
#define FM_EXGPA1	0x0020		/* extended-group-addressing bit 1 */
#define FM_DISCRY	0x0040		/* disable-carry bit */
					/* SN3: reserved */
#define FM_SELRA	0x0080		/* select input from PHY (1=RA,0=RB) */

#define FM_ADDET	0x0700		/* address detection */
#define FM_MDAMA	(0<<8)		/* address detection : DA = MA */
#define FM_MDASAMA	(1<<8)		/* address detection : DA=MA||SA=MA */
#define	FM_MRNNSAFNMA	(2<<8)		/* rec. non-NSA frames DA=MA&&SA!=MA */
#define	FM_MRNNSAF	(3<<8)		/* rec. non-NSA frames DA = MA */
#define	FM_MDISRCV	(4<<8)		/* disable receive function */
#define	FM_MRES0	(5<<8)		/* reserve */
#define	FM_MLIMPROM	(6<<8)		/* limited-promiscuous mode */
#define FM_MPROMISCOUS	(7<<8)		/* address detection : promiscous */

#define FM_SELSA	0x0800		/* select-short-address bit */

#define FM_MMODE	0x7000		/* mode select */
#define FM_MINIT	(0<<12)		/* initialize */
#define FM_MMEMACT	(1<<12)		/* memory activate */
#define FM_MONLINESP	(2<<12)		/* on-line special */
#define FM_MONLINE	(3<<12)		/* on-line (FDDI operational mode) */
#define FM_MILOOP	(4<<12)		/* internal loopback */
#define FM_MRES1	(5<<12)		/* reserved */
#define FM_MRES2	(6<<12)		/* reserved */
#define FM_MELOOP	(7<<12)		/* external loopback */

#define	FM_SNGLFRM	0x8000		/* single-frame-receive mode */
					/* SN3: reserved */

#define	MDR1INIT	(FM_MINIT | FM_MDAMA)

/*
 * Mode Register 2 (MDREG2)
 */
#define	FM_AFULL	0x000f		/* 4-bit value (empty loc.in txqueue)*/
#define	FM_RCVERR	0x0010		/* rec.-errored-frames bit */
#define	FM_SYMCTL	0x0020		/* sysmbol-control bit */
					/* SN3: reserved */
#define	FM_SYNPRQ	0x0040		/* synchron.-NP-DMA-request bit */
#define	FM_ENNPRQ	0x0080		/* enable-NP-DMA-request bit */
#define	FM_ENHSRQ	0x0100		/* enable-host-request bit */
#define	FM_RXFBB01	0x0600		/* rec. frame byte boundary bit0 & 1 */
#define	FM_LSB		0x0800		/* determ. ordering of bytes in buffer*/
#define	FM_PARITY	0x1000		/* 1 = even, 0 = odd */
#define	FM_CHKPAR	0x2000		/* 1 = parity of 32-bit buffer BD-bus*/
#define	FM_STRPFCS	0x4000		/* 1 = strips FCS field of rec.frame */
#define	FM_BMMODE	0x8000		/* Buffer-Memory-Mode (1 = tag mode) */
					/* SN3: 1 = tag, 0 = modified tag */

/*
 * Status Register 1, Upper 16 Bits (ST1U)
 */
#define FM_STEFRMS	0x0001		/* transmit end of frame: synchr. qu.*/
#define FM_STEFRMA0	0x0002		/* transmit end of frame: asyn. qu.0 */
#define FM_STEFRMA1	0x0004		/* transmit end of frame: asyn. qu.1 */
#define FM_STEFRMA2	0x0008		/* transmit end of frame: asyn. qu.2 */
					/* SN3: reserved */
#define FM_STECFRMS	0x0010		/* transmit end of chain of syn. qu. */
					/* SN3: reserved */
#define FM_STECFRMA0	0x0020		/* transmit end of chain of asyn. q0 */
					/* SN3: reserved */
#define FM_STECFRMA1	0x0040		/* transmit end of chain of asyn. q1 */
					/* SN3: STECMDA1 */
#define FM_STECMDA1	0x0040		/* SN3: 'no description' */
#define FM_STECFRMA2	0x0080		/* transmit end of chain of asyn. q2 */
					/* SN3: reserved */
#define	FM_STEXDONS	0x0100		/* transmit until XDONE in syn. qu. */
#define	FM_STBFLA	0x0200		/* asynchr.-queue trans. buffer full */
#define	FM_STBFLS	0x0400		/* synchr.-queue transm. buffer full */
#define	FM_STXABRS	0x0800		/* synchr. queue transmit-abort */
#define	FM_STXABRA0	0x1000		/* asynchr. queue 0 transmit-abort */
#define	FM_STXABRA1	0x2000		/* asynchr. queue 1 transmit-abort */
#define	FM_STXABRA2	0x4000		/* asynchr. queue 2 transmit-abort */
					/* SN3: reserved */
#define	FM_SXMTABT	0x8000		/* transmit abort */

/*
 * Status Register 1, Lower 16 Bits (ST1L)
 */
#define FM_SQLCKS	0x0001		/* queue lock for synchr. queue */
#define FM_SQLCKA0	0x0002		/* queue lock for asynchr. queue 0 */
#define FM_SQLCKA1	0x0004		/* queue lock for asynchr. queue 1 */
#define FM_SQLCKA2	0x0008		/* queue lock for asynchr. queue 2 */
					/* SN3: reserved */
#define FM_STXINFLS	0x0010		/* transmit instruction full: syn. */
					/* SN3: reserved */
#define FM_STXINFLA0	0x0020		/* transmit instruction full: asyn.0 */
					/* SN3: reserved */
#define FM_STXINFLA1	0x0040		/* transmit instruction full: asyn.1 */
					/* SN3: reserved */
#define FM_STXINFLA2	0x0080		/* transmit instruction full: asyn.2 */
					/* SN3: reserved */
#define FM_SPCEPDS	0x0100		/* parity/coding error: syn. queue */
#define FM_SPCEPDA0	0x0200		/* parity/coding error: asyn. queue0 */
#define FM_SPCEPDA1	0x0400		/* parity/coding error: asyn. queue1 */
#define FM_SPCEPDA2	0x0800		/* parity/coding error: asyn. queue2 */
					/* SN3: reserved */
#define FM_STBURS	0x1000		/* transmit buffer underrun: syn. q. */
#define FM_STBURA0	0x2000		/* transmit buffer underrun: asyn.0 */
#define FM_STBURA1	0x4000		/* transmit buffer underrun: asyn.1 */
#define FM_STBURA2	0x8000		/* transmit buffer underrun: asyn.2 */
					/* SN3: reserved */

/*
 * Status Register 2, Upper 16 Bits (ST2U)
 */
#define FM_SOTRBEC	0x0001		/* other beacon received */
#define FM_SMYBEC	0x0002		/* my beacon received */
#define FM_SBEC		0x0004		/* beacon state entered */
#define FM_SLOCLM	0x0008		/* low claim received */
#define FM_SHICLM	0x0010		/* high claim received */
#define FM_SMYCLM	0x0020		/* my claim received */
#define FM_SCLM		0x0040		/* claim state entered */
#define FM_SERRSF	0x0080		/* error in special frame */
#define FM_SNFSLD	0x0100		/* NP and FORMAC+ simultaneous load */
#define FM_SRFRCTOV	0x0200		/* receive frame counter overflow */
					/* SN3: reserved */
#define FM_SRCVFRM	0x0400		/* receive frame */
					/* SN3: reserved */
#define FM_SRCVOVR	0x0800		/* receive FIFO overflow */
#define FM_SRBFL	0x1000		/* receive buffer full */
#define FM_SRABT	0x2000		/* receive abort */
#define FM_SRBMT	0x4000		/* receive buffer empty */
#define FM_SRCOMP	0x8000		/* receive complete. Nontag mode */

/*
 * Status Register 2, Lower 16 Bits (ST2L)
 * Attention: SN3 docu shows these bits the other way around
 */
#define FM_SRES0	0x0001		/* reserved */
#define FM_SESTRIPTK	0x0001		/* SN3: 'no description' */
#define FM_STRTEXR	0x0002		/* TRT expired in claim | beacon st. */
#define FM_SDUPCLM	0x0004		/* duplicate claim received */
#define FM_SSIFG	0x0008		/* short interframe gap */
#define FM_SFRMCTR	0x0010		/* frame counter overflow */
#define FM_SERRCTR	0x0020		/* error counter overflow */
#define FM_SLSTCTR	0x0040		/* lost counter overflow */
#define FM_SPHINV	0x0080		/* PHY invalid */
#define FM_SADET	0x0100		/* address detect */
#define FM_SMISFRM	0x0200		/* missed frame */
#define FM_STRTEXP	0x0400		/* TRT expired and late count > 0 */
#define FM_STVXEXP	0x0800		/* TVX expired */
#define FM_STKISS	0x1000		/* token issued */
#define FM_STKERR	0x2000		/* token error */
#define FM_SMULTDA	0x4000		/* multiple destination address */
#define FM_SRNGOP	0x8000		/* ring operational */

/*
 * Supernet 3:
 * Status Register 3, Upper 16 Bits (ST3U)
 */
#define	FM_SRQUNLCK1	0x0001		/* receive queue unlocked queue 1 */
#define	FM_SRQUNLCK2	0x0002		/* receive queue unlocked queue 2 */
#define	FM_SRPERRQ1	0x0004		/* receive parity error rx queue 1 */
#define	FM_SRPERRQ2	0x0008		/* receive parity error rx queue 2 */
					/* Bit 4-10: reserved */
#define	FM_SRCVOVR2	0x0800		/* receive FIFO overfull rx queue 2 */
#define	FM_SRBFL2	0x1000		/* receive buffer full rx queue 2 */
#define	FM_SRABT2	0x2000		/* receive abort rx queue 2 */
#define	FM_SRBMT2	0x4000		/* receive buf empty rx queue 2 */
#define	FM_SRCOMP2	0x8000		/* receive comp rx queue 2 */

/*
 * Supernet 3:
 * Status Register 3, Lower 16 Bits (ST3L)
 */
#define	FM_AF_BIST_DONE		0x0001	/* Address Filter BIST is done */
#define	FM_PLC_BIST_DONE	0x0002	/* internal PLC Bist is done */
#define	FM_PDX_BIST_DONE	0x0004	/* PDX BIST is done */
					/* Bit  3: reserved */
#define	FM_SICAMDAMAT		0x0010	/* Status internal CAM DA match */
#define	FM_SICAMDAXACT		0x0020	/* Status internal CAM DA exact match */
#define	FM_SICAMSAMAT		0x0040	/* Status internal CAM SA match */
#define	FM_SICAMSAXACT		0x0080	/* Status internal CAM SA exact match */

/*
 * MAC State-Machine Register FM_STMCHN
 */
#define	FM_MDRTAG	0x0004		/* tag bit of long word read */
#define	FM_SNPPND	0x0008		/* r/w from buffer mem. is pending */
#define	FM_TXSTAT	0x0070		/* transmitter state machine state */
#define	FM_RCSTAT	0x0380		/* receiver state machine state */
#define	FM_TM01		0x0c00		/* indicate token mode */
#define	FM_SIM		0x1000		/* indicate send immediate-mode */
#define	FM_REV		0xe000		/* FORMAC Plus revision number */

/*
 * Supernet 3
 * Mode Register 3
 */
#define	FM_MENRS	0x0001		/* Ena enhanced rec status encoding */
#define	FM_MENXS	0x0002		/* Ena enhanced xmit status encoding */
#define	FM_MENXCT	0x0004		/* Ena EXACT/INEXACT matching */
#define	FM_MENAFULL	0x0008		/* Ena enh QCTRL encoding for AFULL */
#define	FM_MEIND	0x0030		/* Ena enh A,C indicator settings */
#define	FM_MENQCTRL	0x0040		/* Ena enh QCTRL encoding */
#define	FM_MENRQAUNLCK	0x0080		/* Ena rec q auto unlock */
#define	FM_MENDAS	0x0100		/* Ena DAS connections by cntr MUX */
#define	FM_MENPLCCST	0x0200		/* Ena Counter Segm test in PLC blck */
#define	FM_MENSGLINT	0x0400		/* Ena Vectored Interrupt reading */
#define	FM_MENDRCV	0x0800		/* Ena dual receive queue operation */
#define	FM_MENFCLOC	0x3000		/* Ena FC location within frm data */
#define	FM_MENTRCMD	0x4000		/* Ena ASYNC1 xmit only after command */
#define	FM_MENTDLPBK	0x8000		/* Ena TDAT to RDAT lkoopback */

/*
 * Supernet 3
 * Frame Selection Register
 */
#define	FM_RECV1	0x000f		/* options for receive queue 1 */
#define	FM_RCV1_ALL	(0<<0)		/* receive all frames */
#define	FM_RCV1_LLC	(1<<0)		/* rec all LLC frames */
#define	FM_RCV1_SMT	(2<<0)		/* rec all SMT frames */
#define	FM_RCV1_NSMT	(3<<0)		/* rec non-SMT frames */
#define	FM_RCV1_IMP	(4<<0)		/* rec Implementor frames */
#define	FM_RCV1_MAC	(5<<0)		/* rec all MAC frames */
#define	FM_RCV1_SLLC	(6<<0)		/* rec all sync LLC frames */
#define	FM_RCV1_ALLC	(7<<0)		/* rec all async LLC frames */
#define	FM_RCV1_VOID	(8<<0)		/* rec all void frames */
#define	FM_RCV1_ALSMT	(9<<0)		/* rec all async LLC & SMT frames */
#define	FM_RECV2	0x00f0		/* options for receive queue 2 */
#define	FM_RCV2_ALL	(0<<4)		/* receive all other frames */
#define	FM_RCV2_LLC	(1<<4)		/* rec all LLC frames */
#define	FM_RCV2_SMT	(2<<4)		/* rec all SMT frames */
#define	FM_RCV2_NSMT	(3<<4)		/* rec non-SMT frames */
#define	FM_RCV2_IMP	(4<<4)		/* rec Implementor frames */
#define	FM_RCV2_MAC	(5<<4)		/* rec all MAC frames */
#define	FM_RCV2_SLLC	(6<<4)		/* rec all sync LLC frames */
#define	FM_RCV2_ALLC	(7<<4)		/* rec all async LLC frames */
#define	FM_RCV2_VOID	(8<<4)		/* rec all void frames */
#define	FM_RCV2_ALSMT	(9<<4)		/* rec all async LLC & SMT frames */
#define	FM_ENXMTADSWAP	0x4000		/* enh rec addr swap (phys -> can) */
#define	FM_ENRCVADSWAP	0x8000		/* enh tx addr swap (can -> phys) */

/*
 * Supernet 3:
 * Address Filter Command Register (AFCMD)
 */
#define	FM_INST		0x0007		/* Address Filter Operation */
#define FM_IINV_CAM	(0<<0)		/* Invalidate CAM */
#define FM_IWRITE_CAM	(1<<0)		/* Write CAM */
#define FM_IREAD_CAM	(2<<0)		/* Read CAM */
#define FM_IRUN_BIST	(3<<0)		/* Run BIST */
#define FM_IFIND	(4<<0)		/* Find */
#define FM_IINV		(5<<0)		/* Invalidate */
#define FM_ISKIP	(6<<0)		/* Skip */
#define FM_ICL_SKIP	(7<<0)		/* Clear all SKIP bits */

/*
 * Supernet 3:
 * Address Filter Status Register (AFSTAT)
 */
					/* Bit  0-4: reserved */
#define	FM_REV_NO	0x00e0		/* Revision Number of Address Filter */
#define	FM_BIST_DONE	0x0100		/* BIST complete */
#define	FM_EMPTY	0x0200		/* CAM empty */
#define	FM_ERROR	0x0400		/* Error (improper operation) */
#define	FM_MULT		0x0800		/* Multiple Match */
#define	FM_EXACT	0x1000		/* Exact Match */
#define	FM_FOUND	0x2000		/* Comparand found in CAM */
#define	FM_FULL		0x4000		/* CAM full */
#define	FM_DONE		0x8000		/* DONE indicator */

/*
 * Supernet 3:
 * BIST Signature Register (AFBIST)
 */
#define	AF_BIST_SIGNAT	0x0553		/* Address Filter BIST Signature */

/*
 * Supernet 3:
 * Personality Register (AFPERS)
 */
#define	FM_VALID	0x0001		/* CAM Entry Valid */
#define	FM_DA		0x0002		/* Destination Address */
#define	FM_DAX		0x0004		/* Destination Address Exact */
#define	FM_SA		0x0008		/* Source Address */
#define	FM_SAX		0x0010		/* Source Address Exact */
#define	FM_SKIP		0x0020		/* Skip this entry */

/*
 * instruction set for command register 1 (NPADDR6-0 = 0x00)
 */
#define FM_IRESET	0x01		/* software reset */
#define FM_IRMEMWI	0x02		/* load Memory Data Reg., inc MARR */
#define FM_IRMEMWO	0x03		/* load MDR from buffer memory, n.i. */
#define FM_IIL		0x04		/* idle/listen */
#define FM_ICL		0x05		/* claim/listen */
#define FM_IBL		0x06		/* beacon/listen */
#define FM_ILTVX	0x07		/* load TVX timer from TVX reg */
#define FM_INRTM	0x08		/* nonrestricted token mode */
#define FM_IENTM	0x09		/* enter nonrestricted token mode */
#define FM_IERTM	0x0a		/* enter restricted token mode */
#define FM_IRTM		0x0b		/* restricted token mode */
#define FM_ISURT	0x0c		/* send unrestricted token */
#define FM_ISRT		0x0d		/* send restricted token */
#define FM_ISIM		0x0e		/* enter send-immediate mode */
#define FM_IESIM	0x0f		/* exit send-immediate mode */
#define FM_ICLLS	0x11		/* clear synchronous queue lock */
#define FM_ICLLA0	0x12		/* clear asynchronous queue 0 lock */
#define FM_ICLLA1	0x14		/* clear asynchronous queue 1 lock */
#define FM_ICLLA2	0x18		/* clear asynchronous queue 2 lock */
					/* SN3: reserved */
#define FM_ICLLR	0x20		/* clear receive queue (SN3:1) lock */
#define FM_ICLLR2	0x21		/* SN3: clear receive queue 2 lock */
#define FM_ITRXBUS	0x22		/* SN3: Tristate X-Bus (SAS only) */
#define FM_IDRXBUS	0x23		/* SN3: drive X-Bus */
#define FM_ICLLAL	0x3f		/* clear all queue locks */

/*
 * instruction set for command register 2 (NPADDR6-0 = 0x01)
 */
#define FM_ITRS		0x01		/* transmit synchronous queue */
					/* SN3: reserved */
#define FM_ITRA0	0x02		/* transmit asynchronous queue 0 */
					/* SN3: reserved */
#define FM_ITRA1	0x04		/* transmit asynchronous queue 1 */
					/* SN3: reserved */
#define FM_ITRA2	0x08		/* transmit asynchronous queue 2 */
					/* SN3: reserved */
#define FM_IACTR	0x10		/* abort current transmit activity */
#define FM_IRSTQ	0x20		/* reset transmit queues */
#define FM_ISTTB	0x30		/* set tag bit */
#define FM_IERSF	0x40		/* enable receive single frame */
					/* SN3: reserved */
#define	FM_ITR		0x50		/* SN3: Transmit Command */


/*
 *	defines for PLC (Am79C864)
 */