supern_2.h

h内核

/******************************************************************************
 *
 *	(C)Copyright 1998,1999 SysKonnect,
 *	a business unit of Schneider & Koch & Co. Datensysteme GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

/*
	defines for AMD Supernet II chip set
	the chips are refered to as
		FPLUS	Formac Plus
		PLC	Physical Layer

	added defines for AMD Supernet III chip set
	added comments on differences between Supernet II and Supernet III
	added defines for the Motorola ELM (MOT_ELM)
*/

#ifndef	_SUPERNET_
#define _SUPERNET_

/*
 * Define Supernet 3 when used
 */
#ifdef	PCI
#ifndef	SUPERNET_3
#define	SUPERNET_3
#endif
#define TAG
#endif

#define	MB	0xff
#define	MW	0xffff
#define	MD	0xffffffff

/*
 * FORMAC frame status (rx_msext)
 */
#define	FS_EI		(1<<2)
#define	FS_AI		(1<<1)
#define	FS_CI		(1<<0)

#define FS_MSVALID	(1<<15)		/* end of queue */
#define FS_MSRABT	(1<<14)		/* frame was aborted during reception*/
#define FS_SSRCRTG	(1<<12)		/* if SA has set MSB (source-routing)*/
#define FS_SEAC2	(FS_EI<<9)	/* error indicator */
#define FS_SEAC1	(FS_AI<<9)	/* address indicator */
#define FS_SEAC0	(FS_CI<<9)	/* copy indicator */
#define FS_SFRMERR	(1<<8)		/* error detected (CRC or length) */
#define FS_SADRRG	(1<<7)		/* address recognized */
#define FS_SFRMTY2	(1<<6)		/* frame-class bit */
#define FS_SFRMTY1	(1<<5)		/* frame-type bit (impementor) */
#define FS_SFRMTY0	(1<<4)		/* frame-type bit (LLC) */
#define FS_ERFBB1	(1<<1)		/* byte offset (depends on LSB bit) */
#define FS_ERFBB0	(1<<0)		/*  - " - */

/*
 * status frame type
 */
#define	FRM_SMT		(0)	/* asynchr. frames */
#define	FRM_LLCA	(1)
#define	FRM_IMPA	(2)	
#define	FRM_MAC		(4)	/* synchr. frames */
#define	FRM_LLCS	(5)
#define	FRM_IMPS	(6)

/*
 * bits in rx_descr.i	(receive frame status word)
 */
#define RX_MSVALID	((long)1<<31)	/* memory status valid */
#define RX_MSRABT	((long)1<<30)	/* memory status receive abort */
#define RX_FS_E		((long)FS_SEAC2<<16)	/* error indicator */
#define RX_FS_A		((long)FS_SEAC1<<16)	/* address indicator */
#define RX_FS_C		((long)FS_SEAC0<<16)	/* copy indicator */
#define RX_FS_CRC	((long)FS_SFRMERR<<16)/* error detected */
#define RX_FS_ADDRESS	((long)FS_SADRRG<<16)	/* address recognized */
#define RX_FS_MAC	((long)FS_SFRMTY2<<16)/* MAC frame */
#define RX_FS_SMT	((long)0<<16)		/* SMT frame */
#define RX_FS_IMPL	((long)FS_SFRMTY1<<16)/* implementer frame */
#define RX_FS_LLC	((long)FS_SFRMTY0<<16)/* LLC frame */

/*
 * receive frame descriptor
 */
union rx_descr {
	struct {
#ifdef	LITTLE_ENDIAN
	unsigned	rx_length :16 ;	/* frame length lower/upper byte */
	unsigned	rx_erfbb  :2 ;	/* received frame byte boundary */
	unsigned	rx_reserv2:2 ;	/* reserved */	
	unsigned	rx_sfrmty :3 ;	/* frame type bits */
	unsigned	rx_sadrrg :1 ;	/* DA == MA or broad-/multicast */
	unsigned	rx_sfrmerr:1 ;	/* received frame not valid */
	unsigned	rx_seac0  :1 ;	/* frame-copied  C-indicator */
	unsigned	rx_seac1  :1 ;	/* address-match A-indicator */
	unsigned	rx_seac2  :1 ;	/* frame-error   E-indicator */
	unsigned	rx_ssrcrtg:1 ;	/* == 1 SA has MSB set */
	unsigned	rx_reserv1:1 ;	/* reserved */	
	unsigned	rx_msrabt :1 ;	/* memory status receive abort */
	unsigned	rx_msvalid:1 ;	/* memory status valid */
#else
	unsigned	rx_msvalid:1 ;	/* memory status valid */
	unsigned	rx_msrabt :1 ;	/* memory status receive abort */
	unsigned	rx_reserv1:1 ;	/* reserved */	
	unsigned	rx_ssrcrtg:1 ;	/* == 1 SA has MSB set */
	unsigned	rx_seac2  :1 ;	/* frame-error   E-indicator */
	unsigned	rx_seac1  :1 ;	/* address-match A-indicator */
	unsigned	rx_seac0  :1 ;	/* frame-copied  C-indicator */
	unsigned	rx_sfrmerr:1 ;	/* received frame not valid */
	unsigned	rx_sadrrg :1 ;	/* DA == MA or broad-/multicast */
	unsigned	rx_sfrmty :3 ;	/* frame type bits */
	unsigned	rx_erfbb  :2 ;	/* received frame byte boundary */
	unsigned	rx_reserv2:2 ;	/* reserved */	
	unsigned	rx_length :16 ;	/* frame length lower/upper byte */
#endif
	} r ;
	long	i ;
} ;

/* defines for Receive Frame Descriptor access */
#define RD_S_ERFBB	0x00030000L	/* received frame byte boundary */
#define RD_S_RES2	0x000c0000L	/* reserved */
#define RD_S_SFRMTY	0x00700000L	/* frame type bits */
#define RD_S_SADRRG	0x00800000L	/* DA == MA or broad-/multicast */
#define RD_S_SFRMERR	0x01000000L	/* received frame not valid */
#define	RD_S_SEAC	0x0e000000L	/* frame status indicators */
#define RD_S_SEAC0	0x02000000L	/* frame-copied  case-indicator */
#define RD_S_SEAC1	0x04000000L	/* address-match A-indicator */
#define RD_S_SEAC2	0x08000000L	/* frame-error   E-indicator */
#define RD_S_SSRCRTG	0x10000000L	/* == 1 SA has MSB set */
#define RD_S_RES1	0x20000000L	/* reserved */
#define RD_S_MSRABT	0x40000000L	/* memory status receive abort */
#define RD_S_MSVALID	0x80000000L	/* memory status valid */

#define	RD_STATUS	0xffff0000L
#define	RD_LENGTH	0x0000ffffL

/* defines for Receive Frames Status Word values */
/*RD_S_SFRMTY*/
#define RD_FRM_SMT	(unsigned long)(0<<20)     /* asynchr. frames */
#define RD_FRM_LLCA	(unsigned long)(1<<20)
#define RD_FRM_IMPA	(unsigned long)(2<<20)
#define RD_FRM_MAC	(unsigned long)(4<<20)     /* synchr. frames */
#define RD_FRM_LLCS	(unsigned long)(5<<20)
#define RD_FRM_IMPS	(unsigned long)(6<<20)

#define TX_DESCRIPTOR	0x40000000L
#define TX_OFFSET_3	0x18000000L

#define TXP1	2

/*
 * transmit frame descriptor
 */
union tx_descr {
	struct {
#ifdef	LITTLE_ENDIAN
	unsigned	tx_length:16 ;	/* frame length lower/upper byte */
	unsigned	tx_res	 :8 ;	/* reserved 	 (bit 16..23) */
	unsigned	tx_xmtabt:1 ;	/* transmit abort */
	unsigned	tx_nfcs  :1 ;	/* no frame check sequence */
	unsigned	tx_xdone :1 ;	/* give up token */
	unsigned	tx_rpxm  :2 ;	/* byte offset */
	unsigned	tx_pat1  :2 ;	/* must be TXP1 */
	unsigned	tx_more	 :1 ;	/* more frame in chain */
#else
	unsigned	tx_more	 :1 ;	/* more frame in chain */
	unsigned	tx_pat1  :2 ;	/* must be TXP1 */
	unsigned	tx_rpxm  :2 ;	/* byte offset */
	unsigned	tx_xdone :1 ;	/* give up token */
	unsigned	tx_nfcs  :1 ;	/* no frame check sequence */
	unsigned	tx_xmtabt:1 ;	/* transmit abort */
	unsigned	tx_res	 :8 ;	/* reserved 	 (bit 16..23) */
	unsigned	tx_length:16 ;	/* frame length lower/upper byte */
#endif
	} t ;
	long	i ;
} ;

/* defines for Transmit Descriptor access */
#define	TD_C_MORE	0x80000000L	/* more frame in chain */
#define	TD_C_DESCR	0x60000000L	/* must be TXP1 */
#define	TD_C_TXFBB	0x18000000L	/* byte offset */
#define	TD_C_XDONE	0x04000000L	/* give up token */
#define TD_C_NFCS	0x02000000L	/* no frame check sequence */
#define TD_C_XMTABT	0x01000000L	/* transmit abort */

#define	TD_C_LNCNU	0x0000ff00L	
#define TD_C_LNCNL	0x000000ffL
#define TD_C_LNCN	0x0000ffffL	/* frame length lower/upper byte */
 
/*
 * transmit pointer
 */
union tx_pointer {
	struct t {
#ifdef	LITTLE_ENDIAN
	unsigned	tp_pointer:16 ;	/* pointer to tx_descr (low/high) */
	unsigned	tp_res	  :8 ;	/* reserved 	 (bit 16..23) */
	unsigned	tp_pattern:8 ;	/* fixed pattern (bit 24..31) */
#else
	unsigned	tp_pattern:8 ;	/* fixed pattern (bit 24..31) */
	unsigned	tp_res	  :8 ;	/* reserved 	 (bit 16..23) */
	unsigned	tp_pointer:16 ;	/* pointer to tx_descr (low/high) */
#endif
	} t ;
	long	i ;
} ;

/* defines for Nontag Mode Pointer access */
#define	TD_P_CNTRL	0xff000000L
#define TD_P_RPXU	0x0000ff00L
#define TD_P_RPXL	0x000000ffL
#define TD_P_RPX	0x0000ffffL


#define TX_PATTERN	0xa0
#define TX_POINTER_END	0xa0000000L
#define TX_INT_PATTERN	0xa0000000L

struct tx_queue {
	struct tx_queue *tq_next ;
	u_short tq_pack_offset ;	/* offset buffer memory */
	u_char  tq_pad[2] ;
} ;

/*
	defines for FORMAC Plus (Am79C830)
*/

/*
 *  FORMAC+ read/write (r/w) registers
 */
#define FM_CMDREG1	0x00		/* write command reg 1 instruction */
#define FM_CMDREG2	0x01		/* write command reg 2 instruction */
#define FM_ST1U		0x00		/* read upper 16-bit of status reg 1 */
#define FM_ST1L		0x01		/* read lower 16-bit of status reg 1 */
#define FM_ST2U		0x02		/* read upper 16-bit of status reg 2 */
#define FM_ST2L		0x03		/* read lower 16-bit of status reg 2 */
#define FM_IMSK1U	0x04		/* r/w upper 16-bit of IMSK 1 */
#define FM_IMSK1L	0x05		/* r/w lower 16-bit of IMSK 1 */
#define FM_IMSK2U	0x06		/* r/w upper 16-bit of IMSK 2 */
#define FM_IMSK2L	0x07		/* r/w lower 16-bit of IMSK 2 */
#define FM_SAID		0x08		/* r/w short addr.-individual */
#define FM_LAIM		0x09		/* r/w long addr.-ind. (MSW of LAID) */
#define FM_LAIC		0x0a		/* r/w long addr.-ind. (middle)*/
#define FM_LAIL		0x0b		/* r/w long addr.-ind. (LSW) */
#define FM_SAGP		0x0c		/* r/w short address-group */
#define FM_LAGM		0x0d		/* r/w long addr.-gr. (MSW of LAGP) */
#define FM_LAGC		0x0e		/* r/w long addr.-gr. (middle) */
#define FM_LAGL		0x0f		/* r/w long addr.-gr. (LSW) */
#define FM_MDREG1	0x10		/* r/w 16-bit mode reg 1 */
#define FM_STMCHN	0x11		/* read state-machine reg */
#define FM_MIR1		0x12		/* read upper 16-bit of MAC Info Reg */
#define FM_MIR0		0x13		/* read lower 16-bit of MAC Info Reg */
#define FM_TMAX		0x14		/* r/w 16-bit TMAX reg */
#define FM_TVX		0x15		/* write 8-bit TVX reg with NP7-0
					   read TVX on NP7-0, timer on NP15-8*/
#define FM_TRT		0x16		/* r/w upper 16-bit of TRT timer */
#define FM_THT		0x17		/* r/w upper 16-bit of THT timer */
#define FM_TNEG		0x18		/* read upper 16-bit of TNEG (TTRT) */
#define FM_TMRS		0x19		/* read lower 5-bit of TNEG,TRT,THT */
			/* F E D C  B A 9 8  7 6 5 4  3 2 1 0
			   x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
#define FM_TREQ0	0x1a		/* r/w 16-bit TREQ0 reg (LSW of TRT) */
#define FM_TREQ1	0x1b		/* r/w 16-bit TREQ1 reg (MSW of TRT) */
#define FM_PRI0		0x1c		/* r/w priority r. for asyn.-queue 0 */
#define FM_PRI1		0x1d		/* r/w priority r. for asyn.-queue 1 */
#define FM_PRI2		0x1e		/* r/w priority r. for asyn.-queue 2 */
#define FM_TSYNC	0x1f		/* r/w 16-bit of the TSYNC register */
#define FM_MDREG2	0x20		/* r/w 16-bit mode reg 2 */
#define FM_FRMTHR	0x21		/* r/w the frame threshold register */
#define FM_EACB		0x22		/* r/w end addr of claim/beacon area */
#define FM_EARV		0x23		/* r/w end addr of receive queue */
/* Supernet 3 */
#define	FM_EARV1	FM_EARV

#define FM_EAS		0x24		/* r/w end addr of synchr. queue */
#define FM_EAA0		0x25		/* r/w end addr of asyn. queue 0 */
#define FM_EAA1		0x26		/* r/w end addr of asyn. queue 1 */
#define FM_EAA2		0x27		/* r/w end addr of asyn. queue 2 */
#define FM_SACL		0x28		/* r/w start addr of claim frame */
#define FM_SABC		0x29		/* r/w start addr of beacon frame */
#define FM_WPXSF	0x2a		/* r/w the write ptr. for special fr.*/
#define FM_RPXSF	0x2b		/* r/w the read ptr. for special fr. */
#define FM_RPR		0x2d		/* r/w the read ptr. for receive qu. */
#define FM_WPR		0x2e		/* r/w the write ptr. for receive qu.*/
#define FM_SWPR		0x2f		/* r/w the shadow wr.-ptr. for rec.q.*/
/* Supernet 3 */ 
#define FM_RPR1         FM_RPR   
#define FM_WPR1         FM_WPR 
#define FM_SWPR1        FM_SWPR

#define FM_WPXS		0x30		/* r/w the write ptr. for synchr. qu.*/
#define FM_WPXA0	0x31		/* r/w the write ptr. for asyn. qu.0 */
#define FM_WPXA1	0x32		/* r/w the write ptr. for asyn. qu.1 */
#define FM_WPXA2	0x33		/* r/w the write ptr. for asyn. qu.2 */
#define FM_SWPXS	0x34		/* r/w the shadow wr.-ptr. for syn.q.*/
#define FM_SWPXA0	0x35		/* r/w the shad. wr.-ptr. for asyn.q0*/
#define FM_SWPXA1	0x36		/* r/w the shad. wr.-ptr. for asyn.q1*/
#define FM_SWPXA2	0x37		/* r/w the shad. wr.-ptr. for asyn.q2*/
#define FM_RPXS		0x38		/* r/w the read ptr. for synchr. qu. */
#define FM_RPXA0	0x39		/* r/w the read ptr. for asyn. qu. 0 */
#define FM_RPXA1	0x3a		/* r/w the read ptr. for asyn. qu. 1 */
#define FM_RPXA2	0x3b		/* r/w the read ptr. for asyn. qu. 2 */
#define FM_MARR		0x3c		/* r/w the memory read addr register */
#define FM_MARW		0x3d		/* r/w the memory write addr register*/
#define FM_MDRU		0x3e		/* r/w upper 16-bit of mem. data reg */
#define FM_MDRL		0x3f		/* r/w lower 16-bit of mem. data reg */

/* following instructions relate to MAC counters and timer */
#define FM_TMSYNC	0x40		/* r/w upper 16 bits of TMSYNC timer */
#define FM_FCNTR	0x41		/* r/w the 16-bit frame counter */
#define FM_LCNTR	0x42		/* r/w the 16-bit lost counter */
#define FM_ECNTR	0x43		/* r/w the 16-bit error counter */

/* Supernet 3:	extensions to old register block */
#define	FM_FSCNTR	0x44		/* r/? Frame Strip Counter */
#define	FM_FRSELREG	0x45		/* r/w Frame Selection Register */

/* Supernet 3:	extensions for 2. receive queue etc. */
#define	FM_MDREG3	0x60		/* r/w Mode Register 3 */
#define	FM_ST3U		0x61		/* read upper 16-bit of status reg 3 */
#define	FM_ST3L		0x62		/* read lower 16-bit of status reg 3 */
#define	FM_IMSK3U	0x63		/* r/w upper 16-bit of IMSK reg 3 */
#define	FM_IMSK3L	0x64		/* r/w lower 16-bit of IMSK reg 3 */
#define	FM_IVR		0x65		/* read Interrupt Vector register */
#define	FM_IMR		0x66		/* r/w Interrupt mask register */
/* 0x67	Hidden */
#define	FM_RPR2		0x68		/* r/w the read ptr. for rec. qu. 2 */
#define	FM_WPR2		0x69		/* r/w the write ptr. for rec. qu. 2 */
#define	FM_SWPR2	0x6a		/* r/w the shadow wptr. for rec. q. 2 */
#define	FM_EARV2	0x6b		/* r/w end addr of rec. qu. 2 */
#define	FM_UNLCKDLY	0x6c		/* r/w Auto Unlock Delay register */
					/* Bit 15-8: RECV2 unlock threshold */
					/* Bit  7-0: RECV1 unlock threshold */
/* 0x6f-0x73	Hidden */
#define	FM_LTDPA1	0x79		/* r/w Last Trans desc ptr for A1 qu. */
/* 0x80-0x9a	PLCS registers of built-in PLCS  (Supernet 3 only) */

/* Supernet 3: Adderss Filter Registers */
#define	FM_AFCMD	0xb0		/* r/w Address Filter Command Reg */
#define	FM_AFSTAT	0xb2		/* r/w Address Filter Status Reg */
#define	FM_AFBIST	0xb4		/* r/w Address Filter BIST signature */
#define	FM_AFCOMP2	0xb6		/* r/w Address Filter Comparand 2 */
#define	FM_AFCOMP1	0xb8		/* r/w Address Filter Comparand 1 */
#define	FM_AFCOMP0	0xba		/* r/w Address Filter Comparand 0 */