skfbi.h

h内核

#define	TST_FRC_APERR_T		(1<<2)	/* Bit 2:  force ADDRPERR on TRG     */
#define	TST_CFG_WRITE_ON	(1<<1)	/* Bit 1:  ena configuration reg. WR */
#define	TST_CFG_WRITE_OFF	(1<<0)	/* Bit 0:  dis configuration reg. WR */

/*	B0_ISRC		32 bit Interrupt source register */
					/* Bit 31..28:	reserved	     */
#define IS_I2C_READY	(1L<<27)	/* Bit 27: (ML)	IRQ on end of I2C tx */
#define IS_IRQ_SW	(1L<<26)	/* Bit 26: (ML)	SW forced IRQ	     */
#define IS_EXT_REG	(1L<<25)	/* Bit 25: (ML) IRQ from external reg*/
#define	IS_IRQ_STAT	(1L<<24)	/* Bit 24:	IRQ status exception */
					/*   PERR, RMABORT, RTABORT DATAPERR */
#define	IS_IRQ_MST_ERR	(1L<<23)	/* Bit 23:	IRQ master error     */
					/*   RMABORT, RTABORT, DATAPERR	     */
#define	IS_TIMINT	(1L<<22)	/* Bit 22:	IRQ_TIMER	*/
#define	IS_TOKEN	(1L<<21)	/* Bit 21:	IRQ_RTM		*/
/*
 * Note: The DAS is our First Port (!=PA)
 */
#define	IS_PLINT1	(1L<<20)	/* Bit 20:	IRQ_PHY_DAS	*/
#define	IS_PLINT2	(1L<<19)	/* Bit 19:	IRQ_IFCP_4	*/
#define	IS_MINTR3	(1L<<18)	/* Bit 18:	IRQ_IFCP_3/IRQ_PHY */
#define	IS_MINTR2	(1L<<17)	/* Bit 17:	IRQ_IFCP_2/IRQ_MAC_2 */
#define	IS_MINTR1	(1L<<16)	/* Bit 16:	IRQ_IFCP_1/IRQ_MAC_1 */
/* Receive Queue 1 */
#define	IS_R1_P		(1L<<15)	/* Bit 15:	Parity Error (q1) */
#define	IS_R1_B		(1L<<14)	/* Bit 14:	End of Buffer (q1) */
#define	IS_R1_F		(1L<<13)	/* Bit 13:	End of Frame (q1) */
#define	IS_R1_C		(1L<<12)	/* Bit 12:	Encoding Error (q1) */
/* Receive Queue 2 */
#define	IS_R2_P		(1L<<11)	/* Bit 11: (DV)	Parity Error (q2) */
#define	IS_R2_B		(1L<<10)	/* Bit 10: (DV)	End of Buffer (q2) */
#define	IS_R2_F		(1L<<9)		/* Bit	9: (DV)	End of Frame (q2) */
#define	IS_R2_C		(1L<<8)		/* Bit	8: (DV)	Encoding Error (q2) */
/* Asynchronous Transmit queue */
					/* Bit  7:	reserved */
#define	IS_XA_B		(1L<<6)		/* Bit	6:	End of Buffer (xa) */
#define	IS_XA_F		(1L<<5)		/* Bit	5:	End of Frame (xa) */
#define	IS_XA_C		(1L<<4)		/* Bit	4:	Encoding Error (xa) */
/* Synchronous Transmit queue */
					/* Bit  3:	reserved */
#define	IS_XS_B		(1L<<2)		/* Bit	2:	End of Buffer (xs) */
#define	IS_XS_F		(1L<<1)		/* Bit	1:	End of Frame (xs) */
#define	IS_XS_C		(1L<<0)		/* Bit	0:	Encoding Error (xs) */

/*
 * Define all valid interrupt source Bits from GET_ISR ()
 */
#define	ALL_IRSR	0x01ffff77L	/* (DV) */
#define	ALL_IRSR_ML	0x0ffff077L	/* (ML) */


/*	B0_IMSK		32 bit Interrupt mask register */
/*
 * The Bit definnition of this register are the same as of the interrupt
 * source register. These definition are directly derived from the Hardware
 * spec.
 */
					/* Bit 31..28:	reserved	     */
#define IRQ_I2C_READY	(1L<<27)	/* Bit 27: (ML)	IRQ on end of I2C tx */
#define IRQ_SW		(1L<<26)	/* Bit 26: (ML)	SW forced IRQ	     */
#define IRQ_EXT_REG	(1L<<25)	/* Bit 25: (ML) IRQ from external reg*/
#define	IRQ_STAT	(1L<<24)	/* Bit 24:	IRQ status exception */
					/*   PERR, RMABORT, RTABORT DATAPERR */
#define	IRQ_MST_ERR	(1L<<23)	/* Bit 23:	IRQ master error     */
					/*   RMABORT, RTABORT, DATAPERR	     */
#define	IRQ_TIMER	(1L<<22)	/* Bit 22:	IRQ_TIMER	*/
#define	IRQ_RTM		(1L<<21)	/* Bit 21:	IRQ_RTM		*/
#define	IRQ_DAS		(1L<<20)	/* Bit 20:	IRQ_PHY_DAS	*/
#define	IRQ_IFCP_4	(1L<<19)	/* Bit 19:	IRQ_IFCP_4	*/
#define	IRQ_IFCP_3	(1L<<18)	/* Bit 18:	IRQ_IFCP_3/IRQ_PHY */
#define	IRQ_IFCP_2	(1L<<17)	/* Bit 17:	IRQ_IFCP_2/IRQ_MAC_2 */
#define	IRQ_IFCP_1	(1L<<16)	/* Bit 16:	IRQ_IFCP_1/IRQ_MAC_1 */
/* Receive Queue 1 */
#define	IRQ_R1_P	(1L<<15)	/* Bit 15:	Parity Error (q1) */
#define	IRQ_R1_B	(1L<<14)	/* Bit 14:	End of Buffer (q1) */
#define	IRQ_R1_F	(1L<<13)	/* Bit 13:	End of Frame (q1) */
#define	IRQ_R1_C	(1L<<12)	/* Bit 12:	Encoding Error (q1) */
/* Receive Queue 2 */
#define	IRQ_R2_P	(1L<<11)	/* Bit 11: (DV)	Parity Error (q2) */
#define	IRQ_R2_B	(1L<<10)	/* Bit 10: (DV)	End of Buffer (q2) */
#define	IRQ_R2_F	(1L<<9)		/* Bit	9: (DV)	End of Frame (q2) */
#define	IRQ_R2_C	(1L<<8)		/* Bit	8: (DV)	Encoding Error (q2) */
/* Asynchronous Transmit queue */
					/* Bit  7:	reserved */
#define	IRQ_XA_B	(1L<<6)		/* Bit	6:	End of Buffer (xa) */
#define	IRQ_XA_F	(1L<<5)		/* Bit	5:	End of Frame (xa) */
#define	IRQ_XA_C	(1L<<4)		/* Bit	4:	Encoding Error (xa) */
/* Synchronous Transmit queue */
					/* Bit  3:	reserved */
#define	IRQ_XS_B	(1L<<2)		/* Bit	2:	End of Buffer (xs) */
#define	IRQ_XS_F	(1L<<1)		/* Bit	1:	End of Frame (xs) */
#define	IRQ_XS_C	(1L<<0)		/* Bit	0:	Encoding Error (xs) */

/* 0x0010 - 0x006b:	formac+ (supernet_3) fequently used registers */
/*	B0_R1_CSR	32 bit BMU control/status reg (rec q 1 ) */
/*	B0_R2_CSR	32 bit BMU control/status reg (rec q 2 ) */
/*	B0_XA_CSR	32 bit BMU control/status reg (a xmit q ) */
/*	B0_XS_CSR	32 bit BMU control/status reg (s xmit q ) */
/* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */

/*	B2_MAC_0	8 bit MAC address Byte 0 */
/*	B2_MAC_1	8 bit MAC address Byte 1 */
/*	B2_MAC_2	8 bit MAC address Byte 2 */
/*	B2_MAC_3	8 bit MAC address Byte 3 */
/*	B2_MAC_4	8 bit MAC address Byte 4 */
/*	B2_MAC_5	8 bit MAC address Byte 5 */
/*	B2_MAC_6	8 bit MAC address Byte 6 (== 0) (DV) */
/*	B2_MAC_7	8 bit MAC address Byte 7 (== 0) (DV) */

/*	B2_CONN_TYP	8 bit Connector type */
/*	B2_PMD_TYP	8 bit PMD type */
/*	Values of connector and PMD type comply to SysKonnect internal std */

/*	The EPROM register are currently of no use */
/*	B2_E_0		8 bit EPROM Byte 0 */
/*	B2_E_1		8 bit EPROM Byte 1 */
/*	B2_E_2		8 bit EPROM Byte 2 */
/*	B2_E_3		8 bit EPROM Byte 3 */

/*	B2_FAR		32 bit Flash-Prom Address Register/Counter */
#define	FAR_ADDR	0x1ffffL	/* Bit 16..0:	FPROM Address mask */

/*	B2_FDP		8 bit Flash-Prom Data Port */

/*	B2_LD_CRTL	8 bit loader control */
/*	Bits are currently reserved */

/*	B2_LD_TEST	8 bit loader test */
#define	LD_T_ON		(1<<3)	/* Bit 3:    Loader Testmode on */
#define	LD_T_OFF	(1<<2)	/* Bit 2:    Loader Testmode off */
#define	LD_T_STEP	(1<<1)	/* Bit 1:    Decrement FPROM addr. Counter */
#define	LD_START	(1<<0)	/* Bit 0:    Start loading FPROM */

/*	B2_TI_INI	32 bit Timer init value */
/*	B2_TI_VAL	32 bit Timer value */
/*	B2_TI_CRTL	8 bit Timer control */
/*	B2_TI_TEST	8 Bit Timer Test */
/*	B2_WDOG_INI	32 bit Watchdog init value */
/*	B2_WDOG_VAL	32 bit Watchdog value */
/*	B2_WDOG_CRTL	8 bit Watchdog control */
/*	B2_WDOG_TEST	8 Bit Watchdog Test */
/*	B2_RTM_INI	32 bit RTM init value */
/*	B2_RTM_VAL	32 bit RTM value */
/*	B2_RTM_CRTL	8 bit RTM control */
/*	B2_RTM_TEST	8 Bit RTM Test */
/*	B2_<TIM>_CRTL	8 bit <TIM> control */
/*	B2_IRQ_MOD_INI	32 bit IRQ Moderation Timer Init Reg.	(ML) */
/*	B2_IRQ_MOD_VAL	32 bit IRQ Moderation Timer Value	(ML) */
/*	B2_IRQ_MOD_CTRL	8 bit IRQ Moderation Timer Control	(ML) */
/*	B2_IRQ_MOD_TEST	8 bit IRQ Moderation Timer Test		(ML) */
#define GET_TOK_CT	(1<<4)	/* Bit 4: Get the Token Counter (RTM) */
#define TIM_RES_TOK	(1<<3)	/* Bit 3: RTM Status: 1 == restricted */
#define TIM_ALARM	(1<<3)	/* Bit 3: Timer Alarm (WDOG) */
#define TIM_START	(1<<2)	/* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/
#define TIM_STOP	(1<<1)	/* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */
#define TIM_CL_IRQ	(1<<0)	/* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
/*	B2_<TIM>_TEST	8 Bit <TIM> Test */
#define	TIM_T_ON	(1<<2)	/* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
#define	TIM_T_OFF	(1<<1)	/* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
#define	TIM_T_STEP	(1<<0)	/* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */

/*	B2_TOK_COUNT	0x014c	(ML)	32 bit	Token Counter */
/*	B2_DESC_ADDR_H	0x0150	(ML)	32 bit	Desciptor Base Addr Reg High */
/*	B2_CTRL_2	0x0154	(ML)	 8 bit	Control Register 2 */
				/* Bit 7..5:	reserved		*/
#define CTRL_CL_I2C_IRQ (1<<4)	/* Bit 4:	Clear I2C IRQ		*/
#define CTRL_ST_SW_IRQ	(1<<3)	/* Bit 3:	Set IRQ SW Request	*/
#define CTRL_CL_SW_IRQ	(1<<2)	/* Bit 2:	Clear IRQ SW Request	*/
#define CTRL_STOP_DONE	(1<<1)	/* Bit 1:	Stop Master is finished */
#define	CTRL_STOP_MAST	(1<<0)	/* Bit 0:	Command Bit to stop the master*/

/*	B2_IFACE_REG	0x0155	(ML)	 8 bit	Interface Register */
				/* Bit 7..3:	reserved		*/
#define	IF_I2C_DATA_DIR	(1<<2)	/* Bit 2:	direction of IF_I2C_DATA*/
#define IF_I2C_DATA	(1<<1)	/* Bit 1:	I2C Data Port		*/
#define	IF_I2C_CLK	(1<<0)	/* Bit 0:	I2C Clock Port		*/

				/* 0x0156:		reserved */
/*	B2_TST_CTRL_2	0x0157	(ML)	 8 bit	Test Control Register 2 */
					/* Bit 7..4:	reserved */
					/* force the following error on */
					/* the next master read/write	*/
#define TST_FRC_DPERR_MR64	(1<<3)	/* Bit 3:	DataPERR RD 64	*/
#define TST_FRC_DPERR_MW64	(1<<2)	/* Bit 2:	DataPERR WR 64	*/
#define TST_FRC_APERR_1M64	(1<<1)	/* Bit 1:	AddrPERR on 1. phase */
#define TST_FRC_APERR_2M64	(1<<0)	/* Bit 0:	AddrPERR on 2. phase */

/*	B2_I2C_CTRL	0x0158	(ML)	32 bit	I2C Control Register	       */
#define	I2C_FLAG	(1L<<31)	/* Bit 31:	Start read/write if WR */
#define I2C_ADDR	(0x7fffL<<16)	/* Bit 30..16:	Addr to be read/written*/
#define	I2C_DEV_SEL	(0x7fL<<9)	/* Bit  9..15:	I2C Device Select      */
					/* Bit  5.. 8:	reserved	       */
#define I2C_BURST_LEN	(1L<<4)		/* Bit  4	Burst Len, 1/4 bytes   */
#define I2C_DEV_SIZE	(7L<<1)		/* Bit	1.. 3:	I2C Device Size	       */
#define I2C_025K_DEV	(0L<<1)		/*		0: 256 Bytes or smaller*/
#define I2C_05K_DEV	(1L<<1)		/* 		1: 512	Bytes	       */
#define	I2C_1K_DEV	(2L<<1)		/*		2: 1024 Bytes	       */
#define I2C_2K_DEV	(3L<<1)		/*		3: 2048	Bytes	       */
#define	I2C_4K_DEV	(4L<<1)		/*		4: 4096 Bytes	       */
#define	I2C_8K_DEV	(5L<<1)		/*		5: 8192 Bytes	       */
#define	I2C_16K_DEV	(6L<<1)		/*		6: 16384 Bytes	       */
#define	I2C_32K_DEV	(7L<<1)		/*		7: 32768 Bytes	       */
#define I2C_STOP_BIT	(1<<0)		/* Bit  0:	Interrupt I2C transfer */

/*
 * I2C Addresses
 *
 * The temperature sensor and the voltage sensor are on the same I2C bus.
 * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1
 *	 in PCI_OUR_REG 1.
 */
#define	I2C_ADDR_TEMP	0x90	/* I2C Address Temperature Sensor */

/*	B2_I2C_DATA	0x015c	(ML)	32 bit	I2C Data Register */

/*	B4_R1_D		4*32 bit current receive Descriptor	(q1) */
/*	B4_R1_DA	32 bit current rec desc address		(q1) */
/*	B4_R1_AC	32 bit current receive Address Count	(q1) */
/*	B4_R1_BC	32 bit current receive Byte Counter	(q1) */
/*	B4_R1_CSR	32 bit BMU Control/Status Register	(q1) */
/*	B4_R1_F		32 bit flag register			(q1) */
/*	B4_R1_T1	32 bit Test Register 1		 	(q1) */
/*	B4_R1_T2	32 bit Test Register 2		 	(q1) */
/*	B4_R1_T3	32 bit Test Register 3		 	(q1) */
/*	B4_R2_D		4*32 bit current receive Descriptor	(q2) */
/*	B4_R2_DA	32 bit current rec desc address		(q2) */
/*	B4_R2_AC	32 bit current receive Address Count	(q2) */
/*	B4_R2_BC	32 bit current receive Byte Counter	(q2) */
/*	B4_R2_CSR	32 bit BMU Control/Status Register	(q2) */
/*	B4_R2_F		32 bit flag register			(q2) */
/*	B4_R2_T1	32 bit Test Register 1			(q2) */
/*	B4_R2_T2	32 bit Test Register 2			(q2) */
/*	B4_R2_T3	32 bit Test Register 3			(q2) */
/*	B5_XA_D		4*32 bit current receive Descriptor	(xa) */
/*	B5_XA_DA	32 bit current rec desc address		(xa) */
/*	B5_XA_AC	32 bit current receive Address Count	(xa) */
/*	B5_XA_BC	32 bit current receive Byte Counter	(xa) */
/*	B5_XA_CSR	32 bit BMU Control/Status Register	(xa) */
/*	B5_XA_F		32 bit flag register			(xa) */
/*	B5_XA_T1	32 bit Test Register 1			(xa) */
/*	B5_XA_T2	32 bit Test Register 2			(xa) */
/*	B5_XA_T3	32 bit Test Register 3			(xa) */
/*	B5_XS_D		4*32 bit current receive Descriptor	(xs) */
/*	B5_XS_DA	32 bit current rec desc address		(xs) */
/*	B5_XS_AC	32 bit current receive Address Count	(xs) */
/*	B5_XS_BC	32 bit current receive Byte Counter	(xs) */
/*	B5_XS_CSR	32 bit BMU Control/Status Register	(xs) */
/*	B5_XS_F		32 bit flag register			(xs) */
/*	B5_XS_T1	32 bit Test Register 1			(xs) */
/*	B5_XS_T2	32 bit Test Register 2			(xs) */
/*	B5_XS_T3	32 bit Test Register 3			(xs) */
/*	B5_<xx>_CSR	32 bit BMU Control/Status Register	(xx) */
#define	CSR_DESC_CLEAR	(1L<<21)    /* Bit 21:	Clear Reset for Descr */
#define	CSR_DESC_SET	(1L<<20)    /* Bit 20:	Set Reset for Descr */
#define	CSR_FIFO_CLEAR	(1L<<19)    /* Bit 19:	Clear Reset for FIFO */
#define	CSR_FIFO_SET	(1L<<18)    /* Bit 18:	Set Reset for FIFO */
#define	CSR_HPI_RUN	(1L<<17)    /* Bit 17:	Release HPI SM */
#define	CSR_HPI_RST	(1L<<16)    /* Bit 16:	Reset HPI SM to Idle */
#define	CSR_SV_RUN	(1L<<15)    /* Bit 15:	Release Supervisor SM */
#define	CSR_SV_RST	(1L<<14)    /* Bit 14:	Reset Supervisor SM */
#define	CSR_DREAD_RUN	(1L<<13)    /* Bit 13:	Release Descr Read SM */
#define	CSR_DREAD_RST	(1L<<12)    /* Bit 12:	Reset Descr Read SM */
#define	CSR_DWRITE_RUN	(1L<<11)    /* Bit 11:	Rel. Descr Write SM */
#define	CSR_DWRITE_RST	(1L<<10)    /* Bit 10:	Reset Descr Write SM */
#define	CSR_TRANS_RUN	(1L<<9)     /* Bit 9:	Release Transfer SM */
#define	CSR_TRANS_RST	(1L<<8)     /* Bit 8:	Reset Transfer SM */
				    /* Bit 7..5: reserved */
#define	CSR_START	(1L<<4)     /* Bit 4:	Start Rec/Xmit Queue */
#define	CSR_IRQ_CL_P	(1L<<3)     /* Bit 3:	Clear Parity IRQ, Rcv */
#define	CSR_IRQ_CL_B	(1L<<2)     /* Bit 2:	Clear EOB IRQ */
#define	CSR_IRQ_CL_F	(1L<<1)     /* Bit 1:	Clear EOF IRQ */
#define	CSR_IRQ_CL_C	(1L<<0)     /* Bit 0:	Clear ERR IRQ */

#define CSR_SET_RESET	(CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
			CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
#define CSR_CLR_RESET	(CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\
			CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)


/*	B5_<xx>_F	32 bit flag register		 (xx) */
					/* Bit 28..31:	reserved	      */
#define F_ALM_FULL	(1L<<27)	/* Bit 27: (ML)	FIFO almost full      */
#define F_FIFO_EOF	(1L<<26)	/* Bit 26: (ML)	Fag bit in FIFO       */
#define F_WM_REACHED	(1L<<25)	/* Bit 25: (ML)	Watermark reached     */
#define F_UP_DW_USED	(1L<<24)	/* Bit 24: (ML) Upper Dword used (bug)*/
					/* Bit 23: 	reserved	      */
#define F_FIFO_LEVEL	(0x1fL<<16)	/* Bit 16..22:(ML) # of Qwords in FIFO*/
					/* Bit  8..15: 	reserved	      */
#define F_ML_WATER_M	0x0000ffL	/* Bit  0.. 7:(ML) Watermark	      */
#define	FLAG_WATER	0x00001fL	/* Bit 4..0:(DV) Level of req data tr.*/

/*	B5_<xx>_T1	32 bit Test Register 1		 (xx) */
/*		Holds four State Machine control Bytes */
#define	SM_CRTL_SV	(0xffL<<24) /* Bit 31..24:  Control Supervisor SM */
#define	SM_CRTL_RD	(0xffL<<16) /* Bit 23..16:  Control Read Desc SM */
#define	SM_CRTL_WR	(0xffL<<8)  /* Bit 15..8:   Control Write Desc SM */
#define	SM_CRTL_TR	(0xffL<<0)  /* Bit 7..0:    Control Transfer SM */

/*	B4_<xx>_T1_TR	8 bit Test Register 1 TR		(xx) */
/*	B4_<xx>_T1_WR	8 bit Test Register 1 WR		(xx) */
/*	B4_<xx>_T1_RD	8 bit Test Register 1 RD		(xx) */
/*	B4_<xx>_T1_SV	8 bit Test Register 1 SV		(xx) */
/* The control status byte of each machine looks like ... */
#define	SM_STATE	0xf0	/* Bit 7..4:	State which shall be loaded */
#define	SM_LOAD		0x08	/* Bit 3:	Load the SM with SM_STATE */
#define	SM_TEST_ON	0x04	/* Bit 2:	Switch on SM Test Mode */
#define	SM_TEST_OFF	0x02	/* Bit 1:	Go off the Test Mode */
#define	SM_STEP		0x01	/* Bit 0:	Step the State Machine */

/* The coding of the states */
#define	SM_SV_IDLE	0x0	/* Supervisor	Idle		Tr/Re	     */
#define	SM_SV_RES_START	0x1	/* Supervisor	Res_Start	Tr/Re	     */
#define	SM_SV_GET_DESC	0x3	/* Supervisor	Get_Desc	Tr/Re	     */
#define	SM_SV_CHECK	0x2	/* Supervisor	Check		Tr/Re	     */
#define	SM_SV_MOV_DATA	0x6	/* Supervisor	Move_Data	Tr/Re	     */
#define	SM_SV_PUT_DESC	0x7	/* Supervisor	Put_Desc	Tr/Re	     */
#define	SM_SV_SET_IRQ	0x5	/* Supervisor	Set_Irq		Tr/Re	     */

#define	SM_RD_IDLE	0x0	/* Read Desc.	Idle		Tr/Re	     */
#define	SM_RD_LOAD	0x1	/* Read Desc.	Load		Tr/Re	     */
#define	SM_RD