skfbi.h

h内核

#endif

#ifndef	TCI
#define	CLI_FBI_SMP(iop)	outp((iop)+IRQ_OTH_DIS,0)
#else
#define	CLI_FBI_SMP(iop)	outp((iop)+IRQ_OTH_DIS,0) ;\
				outp((iop)+IRQ_TC_DIS,0)
#endif

#ifndef UNIX
#define	STI_FBI()	outp(ADDR(IRQ_OTH_EN),0)
#else
#define	STI_FBI(smc)	outp(ADDRS((smc),IRQ_OTH_EN),0)
#endif

/*
 * Terminal count primitives
 */
#define CLI_TCI(smc)	outp(ADDRS((smc),IRQ_TC_DIS),0)
#define STI_TCI(smc)	outp(ADDRS((smc),IRQ_TC_EN),0)
#define CHECK_TC(smc,k)	{(k) = 10000 ;\
	while ((k) && (~inpw(ISR2_A) & IS_TC)) (k)-- ;\
	if (!k) SMT_PANIC(smc,HWM_E0018,HWM_E0018_MSG) ; }

#endif	/* MCA */

#ifdef	ISA

/*
 * address transmission from logic NPADDR6-0 to physical offset address on board
 */
#define FMA(a)	(0x8000|(((a)&0x07)<<1)|(((a)&0x78)<<7))  /* FORMAC+ (r/w) */
#define PRA(a)	(0x1000|(((a)&0x07)<<1)|(((a)&0x18)<<7))  /* PROM (read only)*/
#define P1A(a)	(0x4000|(((a)&0x07)<<1)|(((a)&0x18)<<7))  /* PLC1 (r/w) */
#define P2A(a)	(0x5000|(((a)&0x07)<<1)|(((a)&0x18)<<7))  /* PLC2 (r/w) */
#define TIA(a)	(0x6000|(((a)&0x03)<<1))		  /* Timer (r/w) */

#define	ISRA	0x0000		/* int. source register address (read only) */
#define	ACLA	0x0000		/* address counter low address (write only) */
#define	ACHA	0x0002		/* address counter high address (write only) */
#define	TRCA	0x0004		/* transfer counter address (write only) */
#define	PGRA	0x0006		/* page register address (write only) */
#define RQAA	0x2000		/* Request reg. (write only) */
#define	CSRA	0x3000		/* control/status register address (r/w) */

/*
 * physical address offset + IO-Port base address
 */
#define FM_A(a)	(FMA(a)+smc->hw.iop)	/* FORMAC Plus physical addr */
#define PR_A(a)	(PRA(a)+smc->hw.iop)	/* PROM (read only)*/
#define P1_A(a)	(P1A(a)+smc->hw.iop)	/* PLC1 (r/w) */
#define P2_A(a)	(P2A(a)+smc->hw.iop)	/* PLC2 (r/w) */
#define TI_A(a)	(TIA(a)+smc->hw.iop)	/* Timer (r/w) */

#define	ISR_A	(0x0000+smc->hw.iop) /* int. source register address (read only) */
#define	ACL_A	(0x0000+smc->hw.iop) /* address counter low address (write only) */
#define	ACH_A	(0x0002+smc->hw.iop) /* address counter high address (write only)*/
#define	TRC_A	(0x0004+smc->hw.iop) /* transfer counter address (write only) */
#define	PGR_A	(0x0006+smc->hw.iop) /* page register address (write only) */
#define RQA_A	(0x2000+smc->hw.iop) /* Request reg. (write only) */
#define	CSR_A	(0x3000+smc->hw.iop) /* control/status register address (r/w) */
#ifdef UNIX
#define	CSR_AS(smc) (0x3000+(smc)->hw.iop) /* control/status register address */
#endif
#define	PLC1_I	(0x3400+smc->hw.iop) /* clear PLC1 interrupt bit */
#define	PLC2_I	(0x3800+smc->hw.iop) /* clear PLC2 interrupt bit */

#ifndef	MULT_OEM
#ifndef	OEM_CONCEPT
#define	SKLOGO_STR	"SKFDDI"
#else	/* OEM_CONCEPT */
#define	SKLOGO_STR	OEM_FDDI_LOGO
#endif	/* OEM_CONCEPT */
#endif  /* MULT_OEM */
#define	SADDRL	(24)		/* start address SKLOGO */
#define	SA_MAC	(0)		/* start addr. MAC_AD within the PROM */
#define	PRA_OFF	(0)
#define SA_PMD_TYPE	(8)	/* start addr. PMD-Type */

#define	CDID	(PRA(SADDRL))	/* Card ID int/O port addr. offset */
#define	NEXT_CDID	((PRA(SADDRL+1)) - CDID)

#define	SKFDDI_PSZ	32		/* address PROM size */

#define	READ_PROM(a)	((u_char)inpw(a))
#define	GET_PAGE(i)	outpw(PGR_A,(int)(i))

#define	MAX_PAGES	16		/* 16 pages */
#define	MAX_FADDR	0x2000		/* 8K per page */
#define	VPP_OFF()	outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)))
#define	VPP_ON()	outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)) | \
				CS_VPPSW)

/*
 * control/status register CSRA	bits (log. addr: 0x3000)
 */
/* write */
#define CS_CRESET	0x01		/* Card reset (0=reset) */
#define	CS_IMSK		0x02		/* enable IRQ (1=enable, 0=disable) */
#define CS_RESINT1	0x04		/* PLINT1 reset */
#define	CS_VPPSW	0x10		/* 12V power switch (0=off, 1=on) */
#define CS_BYPASS	0x20		/* bypass switch (0=remove, 1=insert)*/
#define CS_RESINT2	0x40		/* PLINT2 reset */
/* read */
#define	CS_BUSY		0x04		/* master transfer activ (=1) */
#define	CS_SW_EPROM	0x08		/* 0=Application Soft. 1=BOOT-EPROM */
#define	CS_BYSTAT	0x40		/* 0=Bypass exist, 1= ..not */
#define	CS_SAS		0x80		/* single attachement station (=1) */

/*
 * Interrupt source register ISRA (log. addr: 0x0000) read only & low activ.
 */
#define IS_MINTR1	0x01		/* FORMAC ST1U/L && ~IMSK1U/L*/
#define IS_MINTR2	0x02		/* FORMAC ST2U/L && ~IMSK2U/L*/
#define IS_PLINT1	0x04		/* PLC1 */
#define IS_PLINT2	0x08		/* PLC2 */
#define IS_TIMINT	0x10		/* Timer 82C54-2 */

#define	ALL_IRSR	(IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT)

#define	FPROM_SW()	(inpw(CSR_A)&CS_SW_EPROM)
#define	DMA_BUSY()	(inpw(CSR_A)&CS_BUSY)
#define CHECK_FIFO()
#define	BUS_CHECK()

/*
 * set Host Request register (wr.)
 */
#define SET_HRQ(qup)	outpw(RQA_A+((qup)<<1),0)

#ifndef UNIX
#ifndef WINNT
#define	CLI_FBI()	outpw(CSR_A,(inpw(CSR_A)&(CS_CRESET|CS_BYPASS|CS_VPPSW)))
#else
#define	CLI_FBI()	outpw(CSR_A,(l_inpw(CSR_A) & \
				(CS_CRESET|CS_BYPASS|CS_VPPSW)))
#endif
#else
#define	CLI_FBI(smc)	outpw(CSR_AS(smc),(inpw(CSR_AS(smc))& \
						(CS_CRESET|CS_BYPASS|CS_VPPSW)))
#endif

#ifndef UNIX
#define	STI_FBI()	outpw(CSR_A,(inpw(CSR_A) & \
				(CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
#else
#define	STI_FBI(smc)	outpw(CSR_AS(smc),(inpw(CSR_AS(smc)) & \
				(CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
#endif

#define CHECK_DMA()	{unsigned k = 10000 ;\
			while (k && (DMA_BUSY())) k-- ;\
			if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }

#define	GET_ISR()	~inpw(ISR_A)

#endif	/* ISA */

/*--------------------------------------------------------------------------*/
#ifdef	PCI

/*
 *	(DV)	= only defined for Da Vinci
 *	(ML)	= only defined for Monalisa
 */

/*
 * Configuration Space header
 */
#define	PCI_VENDOR_ID	0x00	/* 16 bit	Vendor ID */
#define	PCI_DEVICE_ID	0x02	/* 16 bit	Device ID */
#define	PCI_COMMAND	0x04	/* 16 bit	Command */
#define	PCI_STATUS	0x06	/* 16 bit	Status */
#define	PCI_REV_ID	0x08	/*  8 bit	Revision ID */
#define	PCI_CLASS_CODE	0x09	/* 24 bit	Class Code */
#define	PCI_CACHE_LSZ	0x0c	/*  8 bit	Cache Line Size */
#define	PCI_LAT_TIM	0x0d	/*  8 bit	Latency Timer */
#define	PCI_HEADER_T	0x0e	/*  8 bit	Header Type */
#define	PCI_BIST	0x0f	/*  8 bit	Built-in selftest */
#define	PCI_BASE_1ST	0x10	/* 32 bit	1st Base address */
#define	PCI_BASE_2ND	0x14	/* 32 bit	2nd Base address */
/* Byte 18..2b:	Reserved */
#define	PCI_SUB_VID	0x2c	/* 16 bit	Subsystem Vendor ID */
#define	PCI_SUB_ID	0x2e	/* 16 bit	Subsystem ID */
#define	PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */
/* Byte 34..33:	Reserved */
#define PCI_CAP_PTR	0x34	/*  8 bit (ML)	Capabilities Ptr */
/* Byte 35..3b:	Reserved */
#define	PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */
#define	PCI_IRQ_PIN	0x3d	/*  8 bit	Interrupt Pin */
#define	PCI_MIN_GNT	0x3e	/*  8 bit	Min_Gnt */
#define	PCI_MAX_LAT	0x3f	/*  8 bit	Max_Lat */
/* Device Dependent Region */
#define	PCI_OUR_REG	0x40	/* 32 bit (DV)	Our Register */
#define	PCI_OUR_REG_1	0x40	/* 32 bit (ML)	Our Register 1 */
#define	PCI_OUR_REG_2	0x44	/* 32 bit (ML)	Our Register 2 */
/* Power Management Region */
#define PCI_PM_CAP_ID	0x48	/*  8 bit (ML)	Power Management Cap. ID */
#define PCI_PM_NITEM	0x49	/*  8 bit (ML)	Next Item Ptr */
#define PCI_PM_CAP_REG	0x4a	/* 16 bit (ML)	Power Management Capabilities */
#define PCI_PM_CTL_STS	0x4c	/* 16 bit (ML)	Power Manag. Control/Status */
/* Byte 0x4e:	Reserved */
#define PCI_PM_DAT_REG	0x4f	/*  8 bit (ML)	Power Manag. Data Register */
/* VPD Region */
#define	PCI_VPD_CAP_ID	0x50	/*  8 bit (ML)	VPD Cap. ID */
#define PCI_VPD_NITEM	0x51	/*  8 bit (ML)	Next Item Ptr */
#define PCI_VPD_ADR_REG	0x52	/* 16 bit (ML)	VPD Address Register */
#define PCI_VPD_DAT_REG	0x54	/* 32 bit (ML)	VPD Data Register */
/* Byte 58..ff:	Reserved */

/*
 * I2C Address (PCI Config)
 *
 * Note: The temperature and voltage sensors are relocated on a different
 *	 I2C bus.
 */
#define I2C_ADDR_VPD	0xA0	/* I2C address for the VPD EEPROM */ 

/*
 * Define Bits and Values of the registers
 */
/*	PCI_VENDOR_ID	16 bit	Vendor ID */
/*	PCI_DEVICE_ID	16 bit	Device ID */
/* Values for Vendor ID and Device ID shall be patched into the code */
/*	PCI_COMMAND	16 bit	Command */
#define	PCI_FBTEN	0x0200	/* Bit 9:	Fast Back-To-Back enable */
#define	PCI_SERREN	0x0100	/* Bit 8:	SERR enable */
#define	PCI_ADSTEP	0x0080	/* Bit 7:	Address Stepping */
#define	PCI_PERREN	0x0040	/* Bit 6:	Parity Report Response enable */
#define	PCI_VGA_SNOOP	0x0020	/* Bit 5:	VGA palette snoop */
#define	PCI_MWIEN	0x0010	/* Bit 4:	Memory write an inv cycl ena */
#define	PCI_SCYCEN	0x0008	/* Bit 3:	Special Cycle enable */
#define	PCI_BMEN	0x0004	/* Bit 2:	Bus Master enable */
#define	PCI_MEMEN	0x0002	/* Bit 1:	Memory Space Access enable */
#define	PCI_IOEN	0x0001	/* Bit 0:	IO Space Access enable */

/*	PCI_STATUS	16 bit	Status */
#define	PCI_PERR	0x8000	/* Bit 15:	Parity Error */
#define	PCI_SERR	0x4000	/* Bit 14:	Signaled SERR */
#define	PCI_RMABORT	0x2000	/* Bit 13:	Received Master Abort */
#define	PCI_RTABORT	0x1000	/* Bit 12:	Received Target Abort */
#define	PCI_STABORT	0x0800	/* Bit 11:	Sent Target Abort */
#define	PCI_DEVSEL	0x0600	/* Bit 10..9:	DEVSEL Timing */
#define	PCI_DEV_FAST	(0<<9)	/*		fast */
#define	PCI_DEV_MEDIUM	(1<<9)	/*		medium */
#define	PCI_DEV_SLOW	(2<<9)	/*		slow */
#define	PCI_DATAPERR	0x0100	/* Bit 8:	DATA Parity error detected */
#define	PCI_FB2BCAP	0x0080	/* Bit 7:	Fast Back-to-Back Capability */
#define	PCI_UDF		0x0040	/* Bit 6:	User Defined Features */
#define PCI_66MHZCAP	0x0020	/* Bit 5:	66 MHz PCI bus clock capable */
#define PCI_NEWCAP	0x0010	/* Bit 4:	New cap. list implemented */

#define PCI_ERRBITS	(PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR)

/*	PCI_REV_ID	8 bit	Revision ID */
/*	PCI_CLASS_CODE	24 bit	Class Code */
/*	Byte 2:		Base Class		(02) */
/*	Byte 1:		SubClass		(02) */
/*	Byte 0:		Programming Interface	(00) */

/*	PCI_CACHE_LSZ	8 bit	Cache Line Size */
/*	Possible values: 0,2,4,8,16	*/

/*	PCI_LAT_TIM	8 bit	Latency Timer */

/*	PCI_HEADER_T	8 bit	Header Type */
#define	PCI_HD_MF_DEV	0x80	/* Bit 7:	0= single, 1= multi-func dev */
#define	PCI_HD_TYPE	0x7f	/* Bit 6..0:	Header Layout 0= normal */

/*	PCI_BIST	8 bit	Built-in selftest */
#define	PCI_BIST_CAP	0x80	/* Bit 7:	BIST Capable */
#define	PCI_BIST_ST	0x40	/* Bit 6:	Start BIST */
#define	PCI_BIST_RET	0x0f	/* Bit 3..0:	Completion Code */

/*	PCI_BASE_1ST	32 bit	1st Base address */
#define	PCI_MEMSIZE	0x800L       /* use 2 kB Memory Base */
#define	PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11:	Memory Base Address */
#define	PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4:	Memory Size Req. */
#define	PCI_PREFEN	0x00000008L  /* Bit 3:		Prefetchable */
#define	PCI_MEM_TYP	0x00000006L  /* Bit 2..1:	Memory Type */
#define	PCI_MEM32BIT	(0<<1)	     /* Base addr anywhere in 32 Bit range */
#define	PCI_MEM1M	(1<<1)	     /* Base addr below 1 MegaByte */
#define	PCI_MEM64BIT	(2<<1)	     /* Base addr anywhere in 64 Bit range */
#define	PCI_MEMSPACE	0x00000001L  /* Bit 0:	Memory Space Indic. */

/*	PCI_BASE_2ND	32 bit	2nd Base address */
#define	PCI_IOBASE	0xffffff00L  /* Bit 31..8:  I/O Base address */
#define	PCI_IOSIZE	0x000000fcL  /* Bit 7..2:   I/O Size Requirements */
#define	PCI_IOSPACE	0x00000001L  /* Bit 0:	    I/O Space Indicator */

/*	PCI_SUB_VID	16 bit	Subsystem Vendor ID */
/*	PCI_SUB_ID	16 bit	Subsystem ID */

/*	PCI_BASE_ROM	32 bit	Expansion ROM Base Address */
#define	PCI_ROMBASE	0xfffe0000L  /* Bit 31..17: ROM BASE address (1st) */
#define	PCI_ROMBASZ	0x0001c000L  /* Bit 16..14: Treat as BASE or SIZE */
#define	PCI_ROMSIZE	0x00003800L  /* Bit 13..11: ROM Size Requirements */
#define	PCI_ROMEN	0x00000001L  /* Bit 0:	    Address Decode enable */

/*	PCI_CAP_PTR	8 bit	New Capabilities Pointers */
/*	PCI_IRQ_LINE	8 bit	Interrupt Line */
/*	PCI_IRQ_PIN	8 bit	Interrupt Pin */
/*	PCI_MIN_GNT	8 bit	Min_Gnt */
/*	PCI_MAX_LAT	8 bit	Max_Lat */
/* Device Dependent Region */
/*	PCI_OUR_REG	(DV)	32 bit	Our Register */
/*	PCI_OUR_REG_1	(ML)	32 bit	Our Register 1 */
				  /*	 Bit 31..29:	reserved */
#define	PCI_PATCH_DIR	(3L<<27)  /*(DV) Bit 28..27:	Ext Patchs direction */
#define PCI_PATCH_DIR_0	(1L<<27)  /*(DV) Type of the pins EXT_PATCHS<1..0>   */
#define PCI_PATCH_DIR_1 (1L<<28)  /*	   0 = input			     */
				  /*	   1 = output			     */
#define	PCI_EXT_PATCHS	(3L<<25)  /*(DV) Bit 26..25:	Extended Patches     */
#define PCI_EXT_PATCH_0 (1L<<25)  /*(DV)				     */
#define PCI_EXT_PATCH_1 (1L<<26)  /*	 CLK for MicroWire (ML)		     */
#define PCI_VIO		(1L<<25)  /*(ML)				     */
#define	PCI_EN_BOOT	(1L<<24)  /*	 Bit 24:	Enable BOOT via ROM  */
				  /*	   1 = Don't boot with ROM	     */
				  /*	   0 = Boot with ROM		     */
#define	PCI_EN_IO	(1L<<23)  /*	 Bit 23:	Mapping to IO space  */
#define	PCI_EN_FPROM	(1L<<22)  /*	 Bit 22:	FLASH mapped to mem? */
				  /*	   1 = Map Flash to Memory	     */
			  	  /*	   0 = Disable all addr. decoding    */
#define	PCI_PAGESIZE	(3L<<20)  /*	 Bit 21..20:	FLASH Page Size	     */
#define	PCI_PAGE_16	(0L<<20)  /*		16 k pages		     */