skfbi.h

h内核

#define	PROG_EN		0x80	/* FM1: Vpp prog on/off */
#define	POS_SDR		0x80	/* FM2: Streaming data bit */

/*
 * POS_104
 */
#define	POS_IOSEL	0x3f	/* selected I/O base address */
#define	POS_IRQSEL	0xc0	/* selected interrupt */

/*
 * POS_105
 */
#define	POS_CHCK	0x80
#define POS_SYNC_ERR	0x20	/* FM2: synchronous error reporting	*/
#define POS_PAR_DATA	0x10	/* FM2: data parity enable bit	*/
#define POS_PAR_ADDR	0x08	/* FM2: address parity enable bit	*/
#define	POS_IRQHSEL	0x02	/* FM2: Highest bit for IRQ_selection	*/
#define POS_HARBIT	0x01	/* Highest bit in Bus arbitration selection */

#define	SA_MAC	(0)		/* start addr. MAC_AD within the PROM	*/
#define	PRA_OFF	(0)
#define SA_PMD_TYPE	(8)	/* start addr. PMD-Type	*/

/*
 * address transmission from logical to physical offset address on board
 */
#define	FMA(a)	(0x0100|((a)<<1))	/* FORMAC+ (r/w) */
#define	P2(a)	(0x00c0|((a)<<1))	/* PLC2 (r/w) (DAS) */
#define	P1(a)	(0x0080|((a)<<1))	/* PLC1 (r/w) */
#define	TI(a)	(0x0060|((a)<<1))	/* Timer (r/w) */
#define	PR(a)	(0x0040|((a)<<1))	/* configuration PROM */
#define	CS(a)	(0x0020| (a))		/* control/status */
#define	FF(a)	(0x0010|((a)<<1))	/* FIFO ASIC */
#define	CT(a)	(0x0000|((a)<<1))	/* counter */

/*
 * counter
 */
#define	ACLA	CT(0)		/* address counter low */
#define	ACHA	CT(1)		/* address counter high */
#define	BCN	CT(2)		/* byte counter */
#define	MUX	CT(3)		/* MUX-register */
#define	WCN	CT(0x08)	/* word counter */
#define	FFLG	CT(0x09)	/* FIFO Flags */

/*
 * test/control register (FM2 only)
 */
#define CNT_TST	0x018		/* Counter test control register */
#define CNT_STP 0x01a		/* Counter test step reg. (8 Bit) */

/*
 * CS register (read only)
 */
#define	CSRA	CS(0)		/* control/status register address */
#define	CSFA	CS(2)		/* control/status FIFO BUSY ...	 */
#define	ISRA	CS(4)		/* first int. source register address */
#define	ISR2	CS(6)		/* second int. source register address */
#define	LEDR	CS(0x0c)	/* LED register r/w */
#define	CSIL	CS(0x10)	/* I/O mapped POS_ID_low (100) */
#define	CSIH	CS(0x12)	/*	- " - POS_ID_HIGH (101) */
#define	CSA	CS(0x14)	/*	- " - POS_102 */
#define	CSM	CS(0x0e)	/*	- " - POS_103 */
#define	CSM_FM1	CS(0x16)	/*	- " - POS_103 (copy in FM1) */
#define	CSI	CS(0x18)	/*	- " - POS_104 */
#define	CSS	CS(0x1a)	/*	- " - POS_105 */
#define	CSP_06	CS(0x1c)	/*	- " - POS_106 */
#define	WDOG_ST		0x1c	/* Watchdog status (FM2 only)	*/
#define	WDOG_EN		0x1c	/* Watchdog enabling (FM2 only, 8Bit)	*/
#define	WDOG_DIS	0x1e	/* Watchdog disabling (FM2 only, 8Bit)	*/

#define PGRA	CSM		/* Flash page register */


#define	WCTA	FF(0)		/* word counter */
#define	FFLAG	FF(1)		/* FLAG/V_FULL (FIFO almost full, write only)*/

/*
 * Timer register (FM2 only)
 */
#define RTM_CNT		0x28		/* RTM Counter */
#define TI_DIV		0x60		/* Timer Prescaler */
#define TI_CH1		0x62		/* Timer channel 1 counter */
#define TI_STOP		0x64		/* Stop timer on channel 1 */
#define TI_STRT		0x66		/* Start timer on channel 1 */
#define TI_INI2		0x68		/* Timer: Bus master preemption */
#define TI_CNT2		0x6a		/* Timer */
#define TI_INI3		0x6c		/* Timer: Streaming data */
#define TI_CNT3		0x6e		/* Timer */
#define WDOG_LO		0x70		/* Watchdog counter low */
#define WDOG_HI		0x72		/* Watchdog counter high */
#define RTM_PRE		0x74		/* restr. token prescaler */
#define RTM_TIM		0x76		/* restr. token timer */

/*
 * Recommended Timeout values (for FM2 timer only)
 */
#define TOUT_BM_PRE	188		/* 3.76 usec	*/
#define TOUT_S_DAT	374		/* 7.48 usec	*/

/*
 * CS register (write only)
 */
#define	HSR(p)	CS(0x18|(p))	/* Host request register */

#define	RTM_PUT		0x36		/* restr. token counter write */
#define	RTM_GET		0x28		/*	- " -	clear */
#define	RTM_CLEAR	0x34		/*	- " -	read */

/*
 * BCN	Bit definitions
 */
#define BCN_BUSY	0x8000		/* DMA Busy flag */
#define BCN_AZERO	0x4000		/* Almost zero flag (BCN < 4) */
#define BCN_STREAM	0x2000		/* Allow streaming data (BCN >= 8) */

/*
 * WCN	Bit definitions
 */
#define WCN_ZERO	0x2000		/* Zero flag (counted to zero) */
#define WCN_AZERO	0x1000		/* Almost zero flag (BCN < 4) */

/*
 * CNT_TST	Bit definitions
 */
#define CNT_MODE	0x01		/* Go into test mode */
#define	CNT_D32		0x02		/* 16/32 BIT test mode */

/*
 * FIFO Flag		FIFO Flags/Vfull register
 */
#define FF_VFULL	0x003f		/* V_full value mask */
#define FFLG_FULL	0x2000		/* FULL flag */
#define FFLG_A_FULL	0x1000		/* Almost full flag */
#define FFLG_VFULL	0x0800		/* V_full Flag */
#define FFLG_A_EMP	0x0400		/* almost empty flag */
#define FFLG_EMP	0x0200		/* empty flag */
#define FFLG_T_EMP	0x0100		/* totally empty flag */

/*
 * WDOG		Watchdog status register
 */
#define WDOG_ALM	0x01		/* Watchdog alarm Bit */
#define WDOG_ACT	0x02		/* Watchdog active Bit */

/*
 * CS(0)	CONTROLS
 */
#define	CS_CRESET	0x0001
#define	FIFO_RST	0x0002
#define	CS_IMSK		0x0004
#define	EN_IRQ_CHCK	0x0008
#define	EN_IRQ_TOKEN	0x0010
#define	EN_IRQ_TC	0x0020
#define	TOKEN_STATUS	0x0040
#define	RTM_CHANGE	0x0080

#define	CS_SAS		0x0100
#define	CS_BYSTAT	0x0200	/* bypass connected (0=conn.) */
#define	CS_BYPASS	0x0400	/* bypass on/off indication */

/*
 * CS(2)	FIFOSTAT
 */
#define	HSREQ		0x0007
#define	BIGDIR		0x0008
#define	CSF_BUSY_FIFO	0x0010
#define	CSF_BUSY_DMA	0x0020
#define	SLOT_32		0x0040

#define	LED_0		0x0001
#define	LED_1		0x0002
#define	LED_2		0x0100

#define	MAX_PAGES	8		/* pages */
#define	MAX_FADDR	0x4000		/* 16K per page */

/*
 *	IRQ = ISRA || ISR2 ;
 *
 *	ISRA = IRQ_OTH_EN && (IS_LAN | IS_BUS) ;
 *	ISR2 = IRQ_TC_EN && IS_TC ;
 *
 *	IS_LAN = (IS_MINTR1 | IS_MINTR2 | IS_PLINT1 | IS_PLINT2 | IS_TIMINT) ||
 *		 (IRQ_EN_TOKEN && IS_TOKEN) ;
 *	IS_BUS = IRQ_CHCK_EN && (IS_BUSERR | IS_CHCK_L) ;
 */
/*
 *	ISRA	!!! activ high !!!
 */
#define	IS_MINTR1	0x0001		/* FORMAC ST1U/L & ~IMSK1U/L*/
#define	IS_MINTR2	0x0002		/* FORMAC ST2U/L & ~IMSK2U/L*/
#define	IS_PLINT1	0x0004		/* PLC1 */
#define	IS_PLINT2	0x0008		/* PLC2 */
#define	IS_TIMINT	0x0010		/* Timer 82C54-2 */
#define	IS_TOKEN	0x0020		/* restrictet token monitoring */
#define	IS_CHCK_L	0x0040		/* check line asserted */
#define	IS_BUSERR	0x0080		/* bus error */
/*
 *	ISR2
 */
#define	IS_TC		0x0001		/* terminal count irq */
#define IS_SFDBKRTN	0x0002		/* selected feedback return */
#define IS_D16		0x0004		/* DS16 */
#define	IS_D32		0x0008		/* DS32 */
#define IS_DPEI		0x0010		/* Data Parity Indication */

#define	ALL_IRSR	0x00ff

#define	FM_A(a)	ADDR(FMA(a))	/* FORMAC Plus physical addr */
#define	P1_A(a)	ADDR(P1(a))	/* PLC1 (r/w) */
#define	P2_A(a)	ADDR(P2(a))	/* PLC2 (r/w) (DAS) */
#define	TI_A(a)	ADDR(TI(a))	/* Timer (r/w) FM1 only! */
#define	PR_A(a)	ADDR(PR(a))	/* config. PROM */
#define	CS_A(a)	ADDR(CS(a))	/* control/status */

#define	ISR1_A	ADDR(ISRA)	/* first int. source register address */
#define	ISR2_A	ADDR(ISR2)	/* second	-"-	 */
#define	CSR_A	ADDR(CSRA)	/* control/status register address */
#define	CSF_A	ADDR(CSFA)	/* control/status FIFO BUSY flags (r/w) */

#define	CSIL_A	ADDR(CSIL)	/* I/O mapped POS_ID_low (102) */
#define	CSIH_A	ADDR(CSIH)	/*	- " - POS_ID_HIGH (101) */
#define	CSA_A	ADDR(CSA)	/*	- " - POS_102 */
#define	CSI_A	ADDR(CSI)	/*	- " - POS_104 */
#define	CSM_A	ADDR(CSM)	/*	- " - POS_103 */
#define	CSM_FM1_A	ADDR(CSM_FM1)	/*	- " - POS_103 (2nd copy, FM1) */
#define	CSP_06_A	ADDR(CSP_06)	/*	- " - POS_106 */

#define	WCT_A	ADDR(WCTA)	/* word counter (r/w) */
#define	FFLAG_A	ADDR(FFLAG)	/* FLAG/V_FULL (FIFO almost full, write only)*/

#define	ACL_A	ADDR(ACLA)	/* address counter low */
#define	ACH_A	ADDR(ACHA)	/* address counter high */
#define	BCN_A	ADDR(BCN)	/* byte counter */
#define	MUX_A	ADDR(MUX)	/* MUX-register */

#define	ISR_A	ADDR(ISRA)	/* Interrupt Source Register */
#define	FIFO_RESET_A	ADDR(FIFO_RESET)	/* reset the FIFO */
#define	FIFO_EN_A	ADDR(FIFO_EN)		/* enable the FIFO */

#define WDOG_EN_A	ADDR(WDOG_EN)		/* reset and start the WDOG */
#define WDOG_DIS_A	ADDR(WDOG_DIS)		/* disable the WDOG */
/*
 * all control reg. (read!) are 8 bit (except PAGE_RG_A and LEDR_A)
 */
#define	HSR_A(p)	ADDR(HSR(p))	/* Host request register */

#define	STAT_BYP	0		/* bypass station */
#define	STAT_INS	2		/* insert station */
#define	BYPASS(o)	CS(0x10|(o))	/* o=STAT_BYP || STAT_INS */

#define	IRQ_TC_EN	CS(0x0b)	/* enable/disable IRQ on TC */
#define	IRQ_TC_DIS	CS(0x0a)
#define	IRQ_TOKEN_EN	CS(9)		/* enable/disable IRQ on restr. Token */
#define	IRQ_TOKEN_DIS	CS(8)
#define	IRQ_CHCK_EN	CS(7)		/*	-"-	IRQ after CHCK line */
#define	IRQ_CHCK_DIS	CS(6)
#define	IRQ_OTH_EN	CS(5)		/*	-"-	other IRQ's */
#define	IRQ_OTH_DIS	CS(4)
#define	FIFO_EN		CS(3)		/* disable (reset), enable FIFO */
#define	FIFO_RESET	CS(2)
#define	CARD_EN		CS(1)		/* disable (reset), enable card */
#define	CARD_DIS	CS(0)

#define	LEDR_A		ADDR(LEDR)	/* D0=green, D1=yellow, D8=L2 */
#define	PAGE_RG_A	ADDR(CSM)	/* D<2..0> */
#define	IRQ_CHCK_EN_A	ADDR(IRQ_CHCK_EN)
#define IRQ_CHCK_DIS_A	ADDR(IRQ_CHCK_DIS)

#define	GET_PAGE(bank)	outpw(PAGE_RG_A,(inpw(PAGE_RG_A) &\
				(~POS_PAGE)) |(int) (bank))
#define	VPP_ON()	if (smc->hw.rev == FM1_REV) {	\
				outpw(PAGE_RG_A,	\
				(inpw(PAGE_RG_A) & POS_PAGE) | PROG_EN); \
			}
#define	VPP_OFF()	if (smc->hw.rev == FM1_REV) {	\
				outpw(PAGE_RG_A,(inpw(PAGE_RG_A) & POS_PAGE)); \
			}

#define	SKFDDI_PSZ	16		/* address PROM size */

#define	READ_PROM(a)	((u_char)inp(a))

#define	GET_ISR()	~inpw(ISR1_A)
#ifndef	TCI
#define	CHECK_ISR()	~inpw(ISR1_A)
#define	CHECK_ISR_SMP(iop)	~inpw((iop)+ISRA)
#else
#define	CHECK_ISR()		(~inpw(ISR1_A) | ~inpw(ISR2_A))
#define	CHECK_ISR_SMP(iop)	(~inpw((iop)+ISRA) | ~inpw((iop)+ISR2))
#endif

#define	DMA_BUSY()	(inpw(CSF_A) & CSF_BUSY_DMA)
#define	FIFO_BUSY()	(inpw(CSF_A) & CSF_BUSY_FIFO)
#define	DMA_FIFO_BUSY()	(inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
#define	BUS_CHECK() {	int i ; \
			if ((i = GET_ISR()) & IS_BUSERR) \
				SMT_PANIC(smc,HWM_E0020,HWM_E0020_MSG) ; \
			if (i & IS_CHCK_L) \
				SMT_PANIC(smc,HWM_E0014,HWM_E0014_MSG) ; \
		}

#define	CHECK_DMA() {	u_long k = 10000 ; \
		 while (k && (DMA_BUSY())) { \
			k-- ; \
			BUS_CHECK() ; \
		 } \
		 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }

#define	CHECK_FIFO() {u_long k = 1000000 ;\
		 while (k && (FIFO_BUSY())) k-- ;\
		 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }

#define	CHECK_DMA_FIFO() {u_long k = 1000000 ;\
		 while (k && (DMA_FIFO_BUSY())) { \
			k-- ;\
			BUS_CHECK() ; \
		 } \
		 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }

#ifndef UNIX
#define	CLI_FBI()	outp(ADDR(IRQ_OTH_DIS),0)
#else
#define	CLI_FBI(smc)	outp(ADDRS((smc),IRQ_OTH_DIS),0)