skfbi.h

h内核

/******************************************************************************
 *
 *	(C)Copyright 1998,1999 SysKonnect,
 *	a business unit of Schneider & Koch & Co. Datensysteme GmbH.
 *
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License as published by
 *	the Free Software Foundation; either version 2 of the License, or
 *	(at your option) any later version.
 *
 *	The information in this file is provided "AS IS" without warranty.
 *
 ******************************************************************************/

#ifndef	_SKFBI_H_
#define	_SKFBI_H_

#ifdef SYNC
#define exist_board_far			exist_board
#define get_board_para_far		get_board_para
#endif

/*
 * physical address offset + IO-Port base address
 */
#ifndef	PCI
#define	ADDR(a)	((a)+smc->hw.iop)
#define	ADDRS(smc,a) ((a)+(smc)->hw.iop)
#endif

/*
 * FDDI-Fx (x := {I(SA), E(ISA), M(CA), P(CI)})
 *	address calculation & function defines
 */

#ifdef	EISA

/*
 * Configuration PROM:	 !! all 8-Bit IO's !!
 *					    |<-	  MAC-Address	 ->|
 *	/-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
 * val:	  |PROD_ID0..3|	   | free      |    |00|00|5A|40|    |nn|mm|00|00|
 *	/-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
 * IO-	  ^	      ^	   ^		    ^		     ^
 * port	0C80	    0C83  0C88		   0C90		    0C98
 *	  |	       \
 *	  |		\
 *	  |		 \______________________________________________
 * EISA Expansion Board Product ID:					\
 * BIT:	  |7 6 5 4 3 2 1 0|						 \
 *	  | PROD_ID0	  | PROD_ID1	  | PROD_ID2	  | PROD_ID3	  |
 *	  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 *	  |0| MAN_C0  | MAN_C1	| MAN_C2  | PROD1 | PROD0 | REV1  | REV0  |
 *	  +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 *	   ^=reserved			  | product numb. | revision numb |
 * MAN_Cx = compressed manufacterer code (x:=0..2)
 *	ASCII : 'A'..'Z' : 0x41..0x5A -> compr.(c-0x40) : 0x01..0x1A (5Bits!)
 */

#ifndef	MULT_OEM
#ifndef	OEM_CONCEPT
#define	MAN_C0		('S'-0x40)
#define	MAN_C1		('K'-0x40)
#define	MAN_C2		('D'-0x40)
#define	PROD_ID0	(u_char)((MAN_C0<<2) | (MAN_C1>>3))
#define	PROD_ID1	(u_char)(((MAN_C1<<5) & 0xff) | MAN_C2)
#define	PROD_ID2	(u_char)(1)	/* prod. nr. */
#define	PROD_ID3	(u_char)(0)	/* rev. nr. */

#ifndef	OEM_USER_DATA
#define	OEM_USER_DATA	"SK-NET FDDI V2.0 Userdata"
#endif
#else	/*  OEM_CONCEPT */

/* MAN_C(0|1|2) no longer present (ra). */
#define	PROD_ID0	(u_char)OEM_PROD_ID0
#define	PROD_ID1	(u_char)OEM_PROD_ID1
#define	PROD_ID2	(u_char)OEM_PROD_ID2
#define	PROD_ID3	(u_char)OEM_PROD_ID3
#endif	/* OEM_CONCEPT */

#define	SKLOGO		PROD_ID0, PROD_ID1, PROD_ID2, PROD_ID3
#endif	/* MULT_OEM */

#define	SADDRL	(0)		/* start address SKLOGO */
#define	SA_MAC	(0x10)		/* start addr. MAC_AD within the PROM */
#define	PRA_OFF	(4)
#define SA_PMD_TYPE	(8)	/* start addr. PMD-Type */

#define	SKFDDI_PSZ	32		/* address PROM size */

/*
 * address transmission from logical to physical offset address on board
 */
#define FMA(a)	(0x0400|((a)<<1))	/* FORMAC+ (r/w) */
#define P1A(a)	(0x0800|((a)<<1))	/* PLC1 (r/w) */
#define P2A(a)	(0x0840|((a)<<1))	/* PLC2 (r/w) */
#define TIA(a)	(0x0880|((a)<<1))	/* Timer (r/w) */
#define PRA(a)	(0x0c80| (a))		/* configuration PROM */
#define	C0A(a)	(0x0c84| (a))		/* config. RAM */
#define	C1A(a)	(0x0ca0| (a))		/* IRQ-, DMA-nr., EPROM type */
#define	C2A(a)	(0x0ca4| (a))		/* EPROM and PAGE selector */

#define	CONF	C0A(0)			/* config RAM (card enable bit port) */
#define PGRA	C2A(0)			/* Flash page register */
#define	CDID	PRA(0)			/* Card ID I/O port addr. offset */


/*
 * physical address offset + slot specific IO-Port base address
 */
#define FM_A(a)	(FMA(a)+smc->hw.iop)	/* FORMAC Plus physical addr */
#define P1_A(a)	(P1A(a)+smc->hw.iop)	/* PLC1 (r/w) */
#define P2_A(a)	(P2A(a)+smc->hw.iop)	/* PLC2 (r/w) */
#define TI_A(a)	(TIA(a)+smc->hw.iop)	/* Timer (r/w) */
#define PR_A(a)	(PRA(a)+smc->hw.iop)	/* config. PROM */
#define C0_A(a)	(C0A(a)+smc->hw.iop)	/* config. RAM */
#define C1_A(a)	(C1A(a)+smc->hw.iop)	/* config. RAM */
#define C2_A(a)	(C2A(a)+smc->hw.iop)	/* config. RAM */


#define	CSRA	0x0008		/* control/status register address (r/w) */
#define	ISRA	0x0008		/* int. source register address (upper 8Bits) */
#define PLC1I	0x001a		/* clear PLC1 interrupt (write only) */
#define PLC2I	0x0020		/* clear PLC2 interrupt (write only) */
#define CSFA	0x001c		/* control/status FIFO BUSY flags (read only) */
#define RQAA	0x001c		/* Request reg. (write only) */
#define WCTA	0x001e		/* word counter (r/w) */
#define	FFLAG	0x005e		/* FLAG/V_FULL (FIFO almost full, write only)*/

#define	CSR_A	(CSRA+smc->hw.iop)	/* control/status register address (r/w) */
#ifdef UNIX
#define	CSR_AS(smc)	(CSRA+(smc)->hw.iop)	/* control/status register address (r/w) */
#endif
#define	ISR_A	(ISRA+smc->hw.iop)	/* int. source register address (upper 8Bits) */
#define PLC1_I	(PLC1I+smc->hw.iop)	/* clear PLC1 internupt (write only) */
#define PLC2_I	(PLC2I+smc->hw.iop)	/* clear PLC2 interrupt (write only) */
#define CSF_A	(CSFA+smc->hw.iop)	/* control/status FIFO BUSY flags (r/w) */
#define RQA_A	(RQAA+smc->hw.iop)	/* Request reg. (write only) */
#define WCT_A	(WCTA+smc->hw.iop)	/* word counter (r/w) */
#define	FFLAG_A	(FFLAG+smc->hw.iop)	/* FLAG/V_FULL (FIFO almost full, write only)*/

/*
 * control/status register CSRA	bits
 */
/* write */
#define CS_CRESET	0x01		/* Card reset (0=reset) */
#define	CS_RESET_FIFO	0x02		/* FIFO reset (0=reset) */
#define	CS_IMSK		0x04		/* enable IRQ (1=enable, 0=disable) */
#define	CS_EN_IRQ_TC	0x08		/* enable IRQ from transfer counter */
#define CS_BYPASS	0x20		/* bypass switch (0=remove, 1=insert)*/
#define CS_LED_0	0x40		/* switch LED 0 */
#define	CS_LED_1	0x80		/* switch LED 1 */
/* read */
#define	CS_BYSTAT	0x40		/* 0=Bypass exist, 1= ..not */
#define	CS_SAS		0x80		/* single attachement station (=1) */

/*
 * control/status register CSFA bits (FIFO)
 */
#define	CSF_MUX0	0x01
#define	CSF_MUX1	0x02
#define	CSF_HSREQ0	0x04
#define	CSF_HSREQ1	0x08
#define	CSF_HSREQ2	0x10
#define	CSF_BUSY_DMA	0x40
#define	CSF_BUSY_FIFO	0x80

/*
 * Interrupt source register ISRA (upper 8 data bits) read only & low activ.
 */
#define IS_MINTR1	0x0100		/* FORMAC ST1U/L & ~IMSK1U/L*/
#define IS_MINTR2	0x0200		/* FORMAC ST2U/L & ~IMSK2U/L*/
#define IS_PLINT1	0x0400		/* PLC1 */
#define IS_PLINT2	0x0800		/* PLC2 */
#define IS_TIMINT	0x1000		/* Timer 82C54-2 */
#define	IS_TC		0x2000		/* transf. counter */

#define	ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT|IS_TC)

/*
 * CONFIG<0> RAM (C0_A())
 */
#define	CFG_CARD_EN	0x01		/* card enable */

/*
 * CONFIG<1> RAM (C1_A())
 */
#define	CFG_IRQ_SEL	0x03		/* IRQ select (4 nr.) */
#define	CFG_IRQ_TT	0x04		/* IRQ trigger type (LEVEL/EDGE) */
#define	CFG_DRQ_SEL	0x18		/* DMA requ. (4 nr.) */
#define	CFG_BOOT_EN	0x20		/* 0=BOOT-, 1=Application Software */
#define	CFG_PROG_EN	0x40		/* V_Prog for FLASH_PROM (1=on) */

/*
 * CONFIG<2> RAM (C2_A())
 */
#define	CFG_EPROM_SEL	0x0f		/* FPROM start address selection */
#define	CFG_PAGE	0xf0		/* FPROM page selection */


#define	READ_PROM(a)	((u_char)inp(a))
#define	GET_PAGE(i)	outp(C2_A(0),((int)(i)<<4) | (inp(C2_A(0)) & ~CFG_PAGE))
#define	FPROM_SW()	(inp(C1_A(0)) & CFG_BOOT_EN)

#define	MAX_PAGES	16		/* 16 pages */
#define	MAX_FADDR	0x2000		/* 8K per page */
#define	VPP_ON()	outp(C1_A(0),inp(C1_A(0)) |  CFG_PROG_EN)
#define	VPP_OFF()	outp(C1_A(0),inp(C1_A(0)) & ~CFG_PROG_EN)

#define	DMA_BUSY()	(inpw(CSF_A) & CSF_BUSY_DMA)
#define FIFO_BUSY()	(inpw(CSF_A) & CSF_BUSY_FIFO)
#define	DMA_FIFO_BUSY()	(inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
#define	BUS_CHECK()

#ifdef UNISYS
/* For UNISYS use another macro with drv_usecewait function */
#define CHECK_DMA() {u_long k = 1000000; \
		while (k && (DMA_BUSY())) { k--; drv_usecwait(20); } \
		if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
#else
#define CHECK_DMA() {u_long k = 1000000 ;\
		while (k && (DMA_BUSY())) k-- ;\
		if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
#endif

#define CHECK_FIFO() {u_long k = 1000000 ;\
		while (k && (FIFO_BUSY())) k-- ;\
		if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }

#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
		while (k && (DMA_FIFO_BUSY())) k-- ;\
		if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }

#define	GET_ISR()	~inpw(ISR_A)
#define CHECK_ISR()	~inpw(ISR_A)

#ifndef UNIX
#ifndef	WINNT
#define	CLI_FBI()	outpw(CSR_A,(inpw(CSR_A)&\
			(CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
#else	/* WINNT */
#define CLI_FBI()	outpw(CSR_A,(l_inpw(CSR_A)&\
			(CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
#endif	/* WINNT */
#else	/* UNIX */
#define	CLI_FBI(smc)	outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
			(CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|(smc)->hw.led)
#endif

#ifndef UNIX
#define	STI_FBI()	outpw(CSR_A,(inpw(CSR_A)&\
		(CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|smc->hw.led)
#else
#define	STI_FBI(smc)	outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
		(CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|(smc)->hw.led)
#endif

/* EISA DMA Controller */
#define DMA_WRITE_SINGLE_MASK_BIT_M	0x0a	/* Master DMA Controller */
#define DMA_WRITE_SINGLE_MASK_BIT_S	0xd4	/* Slave DMA Controller */
#define DMA_CLEAR_BYTE_POINTER_M	0x0c
#define DMA_CLEAR_BYTE_POINTER_S	0xd8

#endif	/* EISA */

#ifdef	MCA

/*
 * POS Register:	 !! all I/O's are 8-Bit !!
 */
#define	POS_SYS_SETUP	0x94	/* system setup register */
#define	POS_SYSTEM	0xff	/* system mode */

#define	POS_CHANNEL_POS	0x96	/* register slot ID */
#define	POS_CHANNEL_BIT	0x08	/* mask for -"- */

#define	POS_BASE	0x100	/* POS base address */
#define	POS_ID_LOW	POS_BASE	/* card ID low */
#define	POS_ID_HIGH	(POS_BASE+1)	/* card ID high */
#define	POS_102		(POS_BASE+2)	/* card en., arbitration level .. */
#define	POS_103		(POS_BASE+3)	/* FPROM addr, page */
#define	POS_104		(POS_BASE+4)	/* I/O, IRQ */
#define	POS_105		(POS_BASE+5)	/* POS_CHCK */
#define	POS_106		(POS_BASE+6)	/* to read VPD */
#define	POS_107		(POS_BASE+7)	/* added without function */

/* FM1 card IDs */
#define	FM1_CARD_ID0	0x83
#define	FM1_CARD_ID1	0

#define	FM1_IBM_ID0	0x9c
#define	FM1_IBM_ID1	0x8f


/* FM2 card IDs */
#define	FM2_CARD_ID0	0xab
#define	FM2_CARD_ID1	0

#define	FM2_IBM_ID0	0x7e
#define	FM2_IBM_ID1	0x8f

/* Board revision. */
#define FM1_REV		0
#define FM2_REV		1

#define	MAX_SLOT	8

/*
 * POS_102
 */
#define	POS_CARD_EN	0x01	/* card enable =1 */
#define	POS_SDAT_EN	0x02	/* enable 32-bit streaming data mode */
#define	POS_EN_CHKINT	0x04	/* enable int. from check line asserted */
#define	POS_EN_BUS_ERR	0x08	/* enable int. on invalid busmaster transf. */
#define	POS_FAIRNESS	0x10	/* fairnes on =1 */
/* attention: arbitration level used with bit 0 POS 105 */
#define	POS_LARBIT	0xe0	/* arbitration level	(0,0,0)->level = 0x8
							(1,1,1)->level = 0xf */
/*
 * POS_103
 */
#define	POS_PAGE	0x07	/* FPROM page selection */
#define	POS_BOOT_EN	0x08	/* boot PROM enable =1 */
#define	POS_MSEL	0x70	/* memory start address for FPROM mapping */