tach.h

h内核

/**********************************************************************
 * Defines for the Tachyon Fibre Channel Controller and the Interphase
 * (i)chip TPI. 
 *********************************************************************/

#ifndef _TACH_H
#define _TACH_H

#define MY_PAGE_SIZE       4096
#define REPLICATE          0xFF
#define MAX_NODES          127
#define BROADCAST          0xFFFFFF
#define BROADCAST_ADDR     0xFFFFFFFFFFFF
#define LOGIN_COMPLETED     2
#define LOGIN_ATTEMPTED     1
#define LOGIN_NOT_ATTEMPTED 0
#define TRUE                1
#define FALSE               0

#define TACHYON_LIMIT       0x01EF
#define TACHYON_OFFSET      0x200

/* Offsets to the (i) chip */
#define ICHIP_HW_CONTROL_REG_OFF    (0x080 - TACHYON_OFFSET)
#define ICHIP_HW_STATUS_REG_OFF     (0x084 - TACHYON_OFFSET)
#define ICHIP_HW_ADDR_MASK_REG_OFF  (0x090 - TACHYON_OFFSET)

/* (i)chip Hardware Control Register defines */
#define ICHIP_HCR_RESET         0x01
#define ICHIP_HCR_DERESET       0x0
#define ICHIP_HCR_ENABLE_INTA   0x0000003E 
#define ICHIP_HCR_ENABLE_INTB   0x003E0000
#define ICHIP_HCR_IWDATA_FIFO   0x800000

/* (i)chip Hardware Status Register defines */
#define ICHIP_HSR_INT_LATCH     0x02

/* (i)chip Hardware Address Mask Register defines */
#define ICHIP_HAMR_BYTE_SWAP_ADDR_TR    0x08
#define ICHIP_HAMR_BYTE_SWAP_NO_ADDR_TR 0x04

/* NOVRAM defines */
#define IPH5526_NOVRAM_SIZE 64


/* Offsets for the registers that correspond to the 
 * Qs on the Tachyon (As defined in the Tachyon Manual).
 */

/* Outbound Command Queue (OCQ).
 */
#define OCQ_BASE_REGISTER_OFFSET	0x000  
#define OCQ_LENGTH_REGISTER_OFFSET	0x004
#define OCQ_PRODUCER_REGISTER_OFFSET	0x008  
#define OCQ_CONSUMER_REGISTER_OFFSET	0x00C 

/* Inbound Message Queue (IMQ).
 */
#define IMQ_BASE_REGISTER_OFFSET	0x080
#define IMQ_LENGTH_REGISTER_OFFSET	0x084
#define IMQ_CONSUMER_REGISTER_OFFSET	0x088
#define IMQ_PRODUCER_REGISTER_OFFSET	0x08C

/* Multiframe Sequence Buffer Queue (MFSBQ)
 */
#define MFSBQ_BASE_REGISTER_OFFSET	0x0C0
#define MFSBQ_LENGTH_REGISTER_OFFSET	0x0C4
#define MFSBQ_PRODUCER_REGISTER_OFFSET	0x0C8
#define MFSBQ_CONSUMER_REGISTER_OFFSET	0x0CC  
#define MFS_LENGTH_REGISTER_OFFSET	0x0D0

/* Single Frame Sequence Buffer Queue (SFSBQ)
 */
#define SFSBQ_BASE_REGISTER_OFFSET	0x100
#define SFSBQ_LENGTH_REGISTER_OFFSET	0x104
#define SFSBQ_PRODUCER_REGISTER_OFFSET	0x108
#define SFSBQ_CONSUMER_REGISTER_OFFSET	0x10C  
#define SFS_LENGTH_REGISTER_OFFSET	0x110

/* SCSI Exchange State Table (SEST)
 */
#define SEST_BASE_REGISTER_OFFSET	0x140
#define SEST_LENGTH_REGISTER_OFFSET	0x144
#define SCSI_LENGTH_REGISTER_OFFSET	0x148

/*  Length of the various Qs 
 */
#define NO_OF_ENTRIES		8
#define OCQ_LENGTH		(MY_PAGE_SIZE/32)
#define IMQ_LENGTH		(MY_PAGE_SIZE/32)
#define MFSBQ_LENGTH		8
#define SFSBQ_LENGTH		8
#define SEST_LENGTH		MY_PAGE_SIZE

/* Size of the various buffers.
 */
#define TACH_FRAME_SIZE         2048
#define MFS_BUFFER_SIZE         TACH_FRAME_SIZE
#define SFS_BUFFER_SIZE         (TACH_FRAME_SIZE + TACHYON_HEADER_LEN)
#define SEST_BUFFER_SIZE        512
#define TACH_HEADER_SIZE        64
#define NO_OF_TACH_HEADERS      ((MY_PAGE_SIZE)/TACH_HEADER_SIZE)

#define NO_OF_FCP_CMNDS         (MY_PAGE_SIZE/32)
#define SDB_SIZE                2048
#define NO_OF_SDB_ENTRIES       ((32*MY_PAGE_SIZE)/SDB_SIZE)


/* Offsets to the other Tachyon registers.
 * (As defined in the Tachyon manual)
 */
#define TACHYON_CONFIG_REGISTER_OFFSET          0x184
#define TACHYON_CONTROL_REGISTER_OFFSET         0x188
#define TACHYON_STATUS_REGISTER_OFFSET          0x18C
#define TACHYON_FLUSH_SEST_REGISTER_OFFSET      0x190

/* Defines for the Tachyon Configuration register.
 */
#define SCSI_ENABLE             0x40000000     
#define WRITE_STREAM_SIZE       0x800	/* size = 16 */         
#define READ_STREAM_SIZE        0x300	/* size = 64 */      
#define PARITY_EVEN             0x2         
#define OOO_REASSEMBLY_DISABLE  0x40

/* Defines for the Tachyon Control register.
 */
#define SOFTWARE_RESET	0x80000000
#define OCQ_RESET	0x4
#define ERROR_RELEASE	0x2

/* Defines for the Tachyon Status register.
 */
#define RECEIVE_FIFO_EMPTY      0x10
#define OSM_FROZEN              0x1
#define OCQ_RESET_STATUS        0x20
#define SCSI_FREEZE_STATUS      0x40


/* Offsets to the Frame Manager registers.
 */
#define FMGR_CONFIG_REGISTER_OFFSET 0x1C0
#define FMGR_CONTROL_REGISTER_OFFSET 0x1C4
#define FMGR_STATUS_REGISTER_OFFSET 0x1C8
#define FMGR_TIMER_REGISTER_OFFSET 0x1CC
#define FMGR_WWN_HI_REGISTER_OFFSET 0x1E0
#define FMGR_WWN_LO_REGISTER_OFFSET 0x1E4
#define FMGR_RCVD_ALPA_REGISTER_OFFSET 0x1E8

/* Defines for the Frame Manager Configuration register.
 */
#define BB_CREDIT                    0x10000
#define NPORT                        0x8000 
#define LOOP_INIT_FABRIC_ADDRESS     0x400  
#define LOOP_INIT_PREVIOUS_ADDRESS   0x200  
#define LOOP_INIT_SOFT_ADDRESS       0x80  

/* Defines for the Frame Manager Control register.
 */
#define HOST_CONTROL                 0x02   
#define EXIT_HOST_CONTROL            0x03  
#define OFFLINE                      0x05 
#define INITIALIZE                   0x06 
#define CLEAR_LF                     0x07

/* Defines for the Frame Manager Status register.
 */
#define LOOP_UP                 0x80000000
#define TRANSMIT_PARITY_ERROR   0x40000000
#define NON_PARTICIPATING       0x20000000
#define OUT_OF_SYNC             0x02000000
#define LOSS_OF_SIGNAL          0x01000000
#define NOS_OLS_RECEIVED        0x00080000
#define LOOP_STATE_TIMEOUT      0x00040000
#define LIPF_RECEIVED           0x00020000
#define BAD_ALPA                0x00010000
#define LINK_FAILURE            0x00001000
#define ELASTIC_STORE_ERROR     0x00000400
#define LINK_UP                 0x00000200
#define LINK_DOWN               0x00000100
#define ARBITRATING             0x00000010
#define ARB_WON                 0x00000020
#define OPEN                    0x00000030
#define OPENED                  0x00000040
#define TX_CLS                  0x00000050
#define RX_CLS                  0x00000060
#define TRANSFER                0x00000070
#define INITIALIZING            0x00000080
#define LOOP_FAIL               0x000000D0
#define OLD_PORT                0x000000F0
#define PORT_STATE_ACTIVE       0x0000000F
#define PORT_STATE_OFFLINE      0x00000000
#define PORT_STATE_LF1          0x00000009
#define PORT_STATE_LF2          0x0000000A

/* Completion Message Types 
 * (defined in P.177 of the Tachyon manual)
 */
#define OUTBOUND_COMPLETION             0x000
#define OUTBOUND_COMPLETION_I           0x100
#define OUT_HI_PRI_COMPLETION           0x001
#define OUT_HI_PRI_COMPLETION_I         0x101
#define INBOUND_MFS_COMPLETION          0x102
#define INBOUND_OOO_COMPLETION          0x003
#define INBOUND_SFS_COMPLETION          0x104
#define INBOUND_C1_TIMEOUT              0x105
#define INBOUND_UNKNOWN_FRAME_I         0x106
#define INBOUND_BUSIED_FRAME            0x006
#define SFS_BUF_WARN                    0x107
#define MFS_BUF_WARN                    0x108
#define IMQ_BUF_WARN                    0x109
#define FRAME_MGR_INTERRUPT             0x10A
#define READ_STATUS                     0x10B
#define INBOUND_SCSI_DATA_COMPLETION    0x10C
#define INBOUND_SCSI_COMMAND            0x10D
#define BAD_SCSI_FRAME                  0x10E
#define INB_SCSI_STATUS_COMPLETION      0x10F

/* One of the things that we care about when we receive an
 * Outbound Completion Message (OCM).
 */
#define OCM_TIMEOUT_OR_BAD_ALPA         0x0800

/* Defines for the Tachyon Header structure.
 */
#define SOFI3                0x70
#define SOFN3                0xB0
#define EOFN                 0x5

/* R_CTL */
#define FC4_DEVICE_DATA      0
#define EXTENDED_LINK_DATA   0x20000000
#define FC4_LINK_DATA        0x30000000
#define BASIC_LINK_DATA      0x80000000
#define LINK_CONTROL         0xC0000000
#define SOLICITED_DATA       0x1000000
#define UNSOLICITED_CONTROL  0x2000000
#define SOLICITED_CONTROL    0x3000000
#define UNSOLICITED_DATA     0x4000000